ENTROPY_SRC Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 37.000s 21.888us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 6.000s 52.213us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 30.183us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 10.000s 923.836us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 261.836us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 6.000s 33.231us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 30.183us 20 20 100.00
entropy_src_csr_aliasing 8.000s 261.836us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 37.000s 21.888us 50 50 100.00
entropy_src_rng 7.367m 17.057ms 23 300 7.67
entropy_src_fw_ov 8.933m 20.077ms 184 300 61.33
V2 firmware_mode entropy_src_fw_ov 8.933m 20.077ms 184 300 61.33
V2 rng_mode entropy_src_rng 7.367m 17.057ms 23 300 7.67
V2 rng_max_rate entropy_src_rng_max_rate 10.033m 15.422ms 8 400 2.00
V2 health_checks entropy_src_rng 7.367m 17.057ms 23 300 7.67
V2 conditioning entropy_src_rng 7.367m 17.057ms 23 300 7.67
V2 interrupts entropy_src_rng 7.367m 17.057ms 23 300 7.67
entropy_src_intr 30.000s 200.023us 50 50 100.00
V2 alerts entropy_src_rng 7.367m 17.057ms 23 300 7.67
entropy_src_functional_alerts 29.000s 60.765us 50 50 100.00
V2 stress_all entropy_src_stress_all 6.767m 19.059ms 46 50 92.00
V2 functional_errors entropy_src_functional_errors 8.400m 10.012ms 965 1000 96.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 33.000s 2.469ms 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 14.761us 50 50 100.00
V2 alert_test entropy_src_alert_test 24.000s 102.308us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 476.902us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 476.902us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 6.000s 52.213us 5 5 100.00
entropy_src_csr_rw 5.000s 30.183us 20 20 100.00
entropy_src_csr_aliasing 8.000s 261.836us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 36.471us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 6.000s 52.213us 5 5 100.00
entropy_src_csr_rw 5.000s 30.183us 20 20 100.00
entropy_src_csr_aliasing 8.000s 261.836us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 36.471us 20 20 100.00
V2 TOTAL 1516 2340 64.79
V2S tl_intg_err entropy_src_sec_cm 26.000s 105.929us 5 5 100.00
entropy_src_tl_intg_err 8.000s 123.526us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 7.367m 17.057ms 23 300 7.67
entropy_src_cfg_regwen 28.000s 23.027us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 7.367m 17.057ms 23 300 7.67
V2S sec_cm_config_redun entropy_src_rng 7.367m 17.057ms 23 300 7.67
V2S sec_cm_intersig_mubi entropy_src_rng 7.367m 17.057ms 23 300 7.67
entropy_src_fw_ov 8.933m 20.077ms 184 300 61.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 8.400m 10.012ms 965 1000 96.50
entropy_src_sec_cm 26.000s 105.929us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 8.400m 10.012ms 965 1000 96.50
entropy_src_sec_cm 26.000s 105.929us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 7.367m 17.057ms 23 300 7.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 8.400m 10.012ms 965 1000 96.50
entropy_src_sec_cm 26.000s 105.929us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 8.400m 10.012ms 965 1000 96.50
entropy_src_sec_cm 26.000s 105.929us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 8.400m 10.012ms 965 1000 96.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 29.000s 60.765us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 8.000s 123.526us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.317m 11.604ms 2 50 4.00
V3 TOTAL 2 50 4.00
TOTAL 1698 2570 66.07

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.17 98.15 95.32 98.32 95.50 96.65 96.88 91.01 87.25

Failure Buckets