HMAC Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	12.990s	1.475ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.210s	25.253us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.230s	117.279us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	12.450s	4.378ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.850s	10.844ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.563m	153.189ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.230s	117.279us	20	20	100.00
		hmac_csr_aliasing	7.850s	10.844ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	2.003m	28.093ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.599m	14.563ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.504m	5.426ms	30	30	100.00
		hmac_test_sha384_vectors	9.500m	27.253ms	75	75	100.00
		hmac_test_sha512_vectors	9.160m	12.451ms	75	75	100.00
		hmac_test_hmac256_vectors	16.920s	380.169us	50	50	100.00
		hmac_test_hmac384_vectors	18.770s	431.761us	60	60	100.00
		hmac_test_hmac512_vectors	20.290s	378.496us	75	75	100.00
V2	burst_wr	hmac_burst_wr	40.050s	2.810ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	18.833m	27.969ms	10	10	100.00
V2	error	hmac_error	1.586m	26.175ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.359m	47.709ms	10	10	100.00
V2	save_and_restore	hmac_smoke	12.990s	1.475ms	10	10	100.00
		hmac_long_msg	2.003m	28.093ms	10	10	100.00
		hmac_back_pressure	1.599m	14.563ms	25	25	100.00
		hmac_datapath_stress	18.833m	27.969ms	10	10	100.00
		hmac_burst_wr	40.050s	2.810ms	50	50	100.00
		hmac_stress_all	41.068m	144.129ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	12.990s	1.475ms	10	10	100.00
		hmac_long_msg	2.003m	28.093ms	10	10	100.00
		hmac_back_pressure	1.599m	14.563ms	25	25	100.00
		hmac_datapath_stress	18.833m	27.969ms	10	10	100.00
		hmac_wipe_secret	2.359m	47.709ms	10	10	100.00
		hmac_test_sha256_vectors	4.504m	5.426ms	30	30	100.00
		hmac_test_sha384_vectors	9.500m	27.253ms	75	75	100.00
		hmac_test_sha512_vectors	9.160m	12.451ms	75	75	100.00
		hmac_test_hmac256_vectors	16.920s	380.169us	50	50	100.00
		hmac_test_hmac384_vectors	18.770s	431.761us	60	60	100.00
		hmac_test_hmac512_vectors	20.290s	378.496us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	12.990s	1.475ms	10	10	100.00
		hmac_long_msg	2.003m	28.093ms	10	10	100.00
		hmac_back_pressure	1.599m	14.563ms	25	25	100.00
		hmac_datapath_stress	18.833m	27.969ms	10	10	100.00
		hmac_burst_wr	40.050s	2.810ms	50	50	100.00
		hmac_error	1.586m	26.175ms	10	10	100.00
		hmac_wipe_secret	2.359m	47.709ms	10	10	100.00
		hmac_test_sha256_vectors	4.504m	5.426ms	30	30	100.00
		hmac_test_sha384_vectors	9.500m	27.253ms	75	75	100.00
		hmac_test_sha512_vectors	9.160m	12.451ms	75	75	100.00
		hmac_test_hmac256_vectors	16.920s	380.169us	50	50	100.00
		hmac_test_hmac384_vectors	18.770s	431.761us	60	60	100.00
		hmac_test_hmac512_vectors	20.290s	378.496us	75	75	100.00
		hmac_stress_all	41.068m	144.129ms	50	50	100.00
V2	stress_all	hmac_stress_all	41.068m	144.129ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.130s	16.321us	50	50	100.00
V2	intr_test	hmac_intr_test	1.980s	33.763us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.480s	721.350us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.480s	721.350us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.210s	25.253us	5	5	100.00
		hmac_csr_rw	2.230s	117.279us	20	20	100.00
		hmac_csr_aliasing	7.850s	10.844ms	5	5	100.00
		hmac_same_csr_outstanding	3.200s	166.503us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.210s	25.253us	5	5	100.00
		hmac_csr_rw	2.230s	117.279us	20	20	100.00
		hmac_csr_aliasing	7.850s	10.844ms	5	5	100.00
		hmac_same_csr_outstanding	3.200s	166.503us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.650s	89.538us	5	5	100.00
		hmac_tl_intg_err	5.210s	549.776us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.210s	549.776us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	12.990s	1.475ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.570s	377.660us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	20.404m	137.927ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.040s	561.925us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.97	99.84	97.31	100.00	100.00	99.83	99.52	47.30