I2C Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.433m	4.033ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	37.830s	5.726ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.190s	21.320us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.310s	28.528us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.530s	2.485ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.290s	116.283us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.550s	125.602us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.310s	28.528us	20	20	100.00
		i2c_csr_aliasing	3.290s	116.283us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	11.990s	1.370ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	58.496m	46.037ms	17	50	34.00
V2	host_maxperf	i2c_host_perf	28.859m	50.476ms	50	50	100.00
V2	host_override	i2c_host_override	2.240s	236.627us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.791m	21.342ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.131m	2.433ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.780s	148.219us	50	50	100.00
		i2c_host_fifo_fmt_empty	22.480s	574.105us	50	50	100.00
		i2c_host_fifo_reset_rx	11.520s	924.815us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.386m	7.017ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	39.650s	976.604us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	8.180s	182.939us	21	50	42.00
V2	target_glitch	i2c_target_glitch	16.720s	9.094ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	23.191m	64.593ms	49	50	98.00
V2	target_maxperf	i2c_target_perf	9.050s	924.011us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	59.340s	6.075ms	50	50	100.00
		i2c_target_intr_smoke	12.030s	3.156ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.530s	265.798us	50	50	100.00
		i2c_target_fifo_reset_tx	3.640s	831.790us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	21.863m	67.437ms	50	50	100.00
		i2c_target_stress_rd	59.340s	6.075ms	50	50	100.00
		i2c_target_intr_stress_wr	3.790m	17.041ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	10.820s	2.650ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	4.182m	5.695ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	9.220s	5.079ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	37.840s	10.004ms	20	50	40.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.420s	2.092ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.060s	347.127us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	28.859m	50.476ms	50	50	100.00
		i2c_host_perf_precise	3.526m	23.396ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	39.650s	976.604us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	20.600s	1.698ms	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.550s	650.967us	50	50	100.00
		i2c_target_nack_acqfull_addr	4.690s	1.660ms	50	50	100.00
		i2c_target_nack_txstretch	3.510s	1.251ms	32	50	64.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	25.930s	709.599us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.430s	2.155ms	50	50	100.00
V2	alert_test	i2c_alert_test	2.170s	17.733us	50	50	100.00
V2	intr_test	i2c_intr_test	2.200s	20.912us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.920s	244.504us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.920s	244.504us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.190s	21.320us	5	5	100.00
		i2c_csr_rw	2.310s	28.528us	20	20	100.00
		i2c_csr_aliasing	3.290s	116.283us	5	5	100.00
		i2c_same_csr_outstanding	2.540s	195.276us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.190s	21.320us	5	5	100.00
		i2c_csr_rw	2.310s	28.528us	20	20	100.00
		i2c_csr_aliasing	3.290s	116.283us	5	5	100.00
		i2c_same_csr_outstanding	2.540s	195.276us	20	20	100.00
V2		TOTAL			1672	1792	93.30
V2S	tl_intg_err	i2c_tl_intg_err	3.590s	261.848us	20	20	100.00
		i2c_sec_cm	2.540s	576.917us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.590s	261.848us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	49.650s	4.345ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.910s	1.223ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	46.030s	10.993ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1852	2042	90.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.89	97.19	89.55	74.17	72.02	94.04	98.52	89.75

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 36 failures:

Test i2c_host_stress_all has 23 failures.

1.i2c_host_stress_all.5007105278814954017439577354841771636947745245149969612601815590976515877540
Line 116, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 29167226597 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @396460

2.i2c_host_stress_all.90472391433970049531723784201432964658803119510782699591968651585039587920412
Line 215, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 93068746678 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @8253354

... and 21 more failures.

Test i2c_host_mode_toggle has 13 failures.

4.i2c_host_mode_toggle.31177011228053413529902384508339252438295372440610866113355114847499067709707
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  99753923 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @21111

8.i2c_host_mode_toggle.5493498148251192518901983133257601961671678360988254958346494734309097699158
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 454210671 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @105147

... and 11 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
- Test i2c_target_hrst has 30 failures.
  - 0.i2c_target_hrst.77959118616359573778673193452447806132908803355461506954660907472208149854266
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10170334221 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10170334221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.20057895006091030232609422479760430501545402871474108430135850962040813945017
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10004061580 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10004061580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
- Test i2c_target_unexp_stop has 28 failures.
  - 0.i2c_target_unexp_stop.29040053518084382422386225614585077443939148565565801835430852509866349556433
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 201305227 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 79 [0x4f])
  UVM_INFO @ 201305227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.17796449409183389740820642070439496537486141372991067358377035642356535918831
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  68291222 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 119 [0x77])
  UVM_INFO @  68291222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 26 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 5.i2c_target_stress_all_with_rand_reset.104165650762282177830589104641166846199726934313688701762209842247350663634134
    Line 112, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4362780276 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 73 [0x49])
  UVM_INFO @ 4362780276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.54786036286877274545070083719005868302498125050537266071310846708756173314818
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 117629190 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 117629190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.79873897699114914155862406669704711965746177259287717168008475291420461453233
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1714585739 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1714585739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 8 failures.

0.i2c_target_stress_all_with_rand_reset.108340192000183965481486164563146064704097509669867715430856428961678583977731
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 707397018 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 707397018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.106548936363422645735254257664350995553411275305250625034175979034315625943221
Line 138, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10993430454 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10993430454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
- Test i2c_target_nack_txstretch has 18 failures.
  - 1.i2c_target_nack_txstretch.112601482774962120861596992502346811641894801231599237515284482831987130132222
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 699177768 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 699177768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.i2c_target_nack_txstretch.71382446677084598478627663032298021497555122905760411074790829208177252552364
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 344157898 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 344157898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 15 failures:

Test i2c_host_mode_toggle has 15 failures.

3.i2c_host_mode_toggle.82020951192723141309751810748689435612201100547114316672693597499754380962360
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  58701564 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

7.i2c_host_mode_toggle.26702544607810676546965376302745889129090357446579741399160118182362042565471
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  52854492 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 13 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 12 failures:
- Test i2c_target_unexp_stop has 12 failures.
  - 10.i2c_target_unexp_stop.13345689714445891046920793601441338541436532211269414495424727272964180906760
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  62928787 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  62928787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.i2c_target_unexp_stop.1088447062863546439568963273464587506957505244784330166361756757752187531094
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 321939633 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 321939633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:

Test i2c_target_unexp_stop has 10 failures.

7.i2c_target_unexp_stop.50053220798610946583340024378957354113604769330627142365530843095776820374912
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 395102636 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 395102636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_target_unexp_stop.98852817208871539716037503097786255718218250704042557926612099636418089102744
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 161504906 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 161504906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Job timed out after * minutes has 5 failures:
- Test i2c_host_stress_all has 5 failures.
  - 4.i2c_host_stress_all.112975939596354707708316258391016646177331682709932440712230678903006900351717
    Log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 21.i2c_host_stress_all.91805504119171039876783185876569138475843673099453421530788642857481725018590
    Log /nightly/runs/scratch/master/i2c-sim-vcs/21.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 3 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

7.i2c_host_stress_all.104558577997477824700252491150045852924423153479166941257964339734812923709278
Line 142, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 21054310090 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @11024276

26.i2c_host_stress_all.79771093528091410235399195519817296207910342471498750614536327632173097852328
Line 278, in log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 9684065345 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3320970

... and 3 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 4.i2c_target_stretch.10387369561400155072618451553690627378295004190631132935921071463737128242422
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10007406159 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10007406159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.i2c_target_stretch.60573956861187334397112733145460524222239486378709483446700862808893996062295
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/32.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001042703 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001042703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 5.i2c_target_tx_stretch_ctrl.1474675865308089211254818762099703705287245356979954635905871346431828199791
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 42.i2c_target_tx_stretch_ctrl.101143976926373508014019171137912034973341805924903018438630183892764253698182
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 15.i2c_target_fifo_watermarks_tx.103291163646942287409510344584379965132058400502057318053657850210753576183100
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_intr_stress_wr has 1 failures.
  - 0.i2c_target_intr_stress_wr.45998892797772004624874147971236932914698389633168184680741656689593870086390
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 30097166665 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 30097166665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all has 1 failures.
  - 18.i2c_target_stress_all.44128822101361762405183651455733585595607760883786552680396391257468969823971
    Line 108, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 38024503031 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 38024503031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 9.i2c_target_stress_all_with_rand_reset.20476725342506359563066011038368744813313271037446004437857738707174851847908
    Line 121, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 619668425 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
  UVM_INFO @ 619668425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 9.i2c_host_mode_toggle.89235585850633579191501405945025782349539568037402107771262373918658599415335
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  46085239 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x81bf6e14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  46085239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```