KEYMGR Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	37.440s	7.505ms	50	50	100.00
V1	random	keymgr_random	40.540s	1.677ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.510s	86.927us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.590s	31.399us	15	20	75.00
V1	csr_bit_bash	keymgr_csr_bit_bash	19.500s	3.401ms	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	14.240s	1.389ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.860s	42.043us	13	20	65.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.590s	31.399us	15	20	75.00
		keymgr_csr_aliasing	14.240s	1.389ms	5	5	100.00
V1		TOTAL			142	155	91.61
V2	cfgen_during_op	keymgr_cfg_regwen	1.884m	4.740ms	50	50	100.00
V2	sideload	keymgr_sideload	30.340s	5.811ms	50	50	100.00
		keymgr_sideload_kmac	43.920s	3.090ms	50	50	100.00
		keymgr_sideload_aes	36.370s	5.932ms	50	50	100.00
		keymgr_sideload_otbn	30.690s	1.455ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	21.130s	2.802ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	14.450s	1.203ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.720s	406.286us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	55.240s	9.518ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	22.340s	1.270ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	7.020s	499.850us	50	50	100.00
V2	stress_all	keymgr_stress_all	8.223m	47.072ms	47	50	94.00
V2	intr_test	keymgr_intr_test	2.280s	11.550us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.450s	165.533us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.200s	303.758us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.200s	303.758us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.510s	86.927us	5	5	100.00
		keymgr_csr_rw	2.590s	31.399us	15	20	75.00
		keymgr_csr_aliasing	14.240s	1.389ms	5	5	100.00
		keymgr_same_csr_outstanding	4.920s	327.844us	12	20	60.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.510s	86.927us	5	5	100.00
		keymgr_csr_rw	2.590s	31.399us	15	20	75.00
		keymgr_csr_aliasing	14.240s	1.389ms	5	5	100.00
		keymgr_same_csr_outstanding	4.920s	327.844us	12	20	60.00
V2		TOTAL			728	740	98.38
V2S	sec_cm_additional_check	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
		keymgr_tl_intg_err	7.190s	2.496ms	12	20	60.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.730s	127.154us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.730s	127.154us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.730s	127.154us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.730s	127.154us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.980s	1.689ms	12	20	60.00
V2S	prim_count_check	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.190s	2.496ms	12	20	60.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.730s	127.154us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.884m	4.740ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	40.540s	1.677ms	50	50	100.00
		keymgr_csr_rw	2.590s	31.399us	15	20	75.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	40.540s	1.677ms	50	50	100.00
		keymgr_csr_rw	2.590s	31.399us	15	20	75.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	40.540s	1.677ms	50	50	100.00
		keymgr_csr_rw	2.590s	31.399us	15	20	75.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	14.450s	1.203ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	22.340s	1.270ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	22.340s	1.270ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	40.540s	1.677ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	21.000s	5.330ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	35.130s	4.281ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	14.450s	1.203ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	35.130s	4.281ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	35.130s	4.281ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	35.130s	4.281ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.500s	911.051us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	35.130s	4.281ms	49	50	98.00
V2S		TOTAL			148	165	89.70
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.010s	2.770ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1042	1110	93.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.10	97.95	98.49	100.00	99.01	98.63	91.26

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 37 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 8 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.28325673347924533367870778594971919566087457797630434378543351916399539298691
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @ 157377915 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @ 157377915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_shadow_reg_errors_with_csr_rw.43362514289596280618225044007253180164927995933706878499007105901406117480626
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @   9190849 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @   9190849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_csr_rw has 5 failures.

0.keymgr_csr_rw.76605140446902415968939043487321128033722271319616604506927527276108668029843
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  29315056 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  29315056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_csr_rw.59420077185401730897723307948013347185801131573380534288085854405524351475161
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  19586656 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  19586656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_same_csr_outstanding has 8 failures.

0.keymgr_same_csr_outstanding.74564191428008567449867067298600557551592899177248412958491773585661499969923
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  56372097 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  56372097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_same_csr_outstanding.111641271719576643249388248956040320673106588947864720344709623955911788472958
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  64272573 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  64272573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_tl_intg_err has 8 failures.

1.keymgr_tl_intg_err.85249913370533115914459156506683418893953290554835017584638453673053664195810
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @  43090718 ps: (keymgr_csr_assert_fpv.sv:396) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @  43090718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_tl_intg_err.90964148449305902719317354514944864255896529094981671603119406409722061940353
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @  10871063 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @  10871063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_csr_mem_rw_with_rand_reset has 7 failures.

1.keymgr_csr_mem_rw_with_rand_reset.30523315609418895333582085115937623442608916865357459407738740545523028519018
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @   9444564 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @   9444564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_csr_mem_rw_with_rand_reset.49615274996978375107048610863897170209138756423955717559247697107314756887229
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @  54599983 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @  54599983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test keymgr_stress_all_with_rand_reset has 24 failures.
  - 0.keymgr_stress_all_with_rand_reset.35101489170141368581486309974777351621517512367749175043059044635261936341658
    Line 758, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 239590238 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 239590238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.keymgr_stress_all_with_rand_reset.84693330285041808875776851935019968748348324676836592731248004752901954807622
    Line 173, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 237026000 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 237026000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_custom_cm has 1 failures.

5.keymgr_custom_cm.53355507941072748749437056292165007607689885963452932438183044961880705892092
Line 203, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_custom_cm/latest/run.log

  UVM_ERROR @  79350200 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  79350200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

23.keymgr_stress_all.5622828936140091558155263343963045988324137056829655425487780232280160670410
Line 1589, in log /nightly/runs/scratch/master/keymgr-sim-vcs/23.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1263602398 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 1263602398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.keymgr_stress_all.11911857566260629133610775471441119644334029744681991348722831536856087726296
Line 933, in log /nightly/runs/scratch/master/keymgr-sim-vcs/42.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 525191872 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 525191872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 13.keymgr_stress_all_with_rand_reset.90492064692413402213076531939975664018053320201411749427786092054505722027740
    Line 266, in log /nightly/runs/scratch/master/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 675629532 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 675629532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 24.keymgr_lc_disable.35501182717676308649255211220217999094962606582440580191089629334665493243225
    Line 112, in log /nightly/runs/scratch/master/keymgr-sim-vcs/24.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @   4385663 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @   4385663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 25.keymgr_stress_all.37508363312950152121219220260462371523728672325089034383839203148180259379624
    Line 1416, in log /nightly/runs/scratch/master/keymgr-sim-vcs/25.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 2835506769 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_5
  UVM_INFO @ 2835506769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

45.keymgr_stress_all_with_rand_reset.44646397196070247577570654222738622016365102817997807522450649429139465265813
Line 2472, in log /nightly/runs/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1408340166 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (158372916547025257619584941965798978529375985239388426369229701820407967849884973741231257715581954022304682817010621421239231628475255843028445393048525775462661570160118170188413202295530513284733700956702181602043468168674953666993153649512045798482758046804868871180134535341612905209 [0x42909ab0000000054d487a8fa5a6ec8338515549630dded6728ed74472c08a7d461552bf664ef336fc9ec937c21e4b2dd4ee185477da1d8b55bda80fcc2b3f21de14fdd97c81d97f32acc07232f2be6811498ab6d90259e3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 32405606539563734169482878431259056064598923557757230585975974298563431246255296303753842926589992502214170394951978047880909240440029814912472834747733431125228692793582976467157408840593643486104946327644802404674665291604705719149004909965592334597084832245867103412722404136098986265403031991033 [0xc6334a434038cecb0000000054d487a8fa5a6ec8338515549630dded6728ed74472c08a7d461552bf664ef336fc9ec937c21e4b2dd4ee185477da1d8b55bda80fcc2b3f21de14fdd97c81d97f32acc07232f2be6811498ab6d90259e3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation

   HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
   RomDigest act: 0xb55bda80fcc2b3f21de14fdd97c81d97f32acc07232f2be6811498ab6d90259e, exp: 0xb55bda80fcc2b3f21de14fdd97c81d97f32acc07232f2be6811498ab6d90259e
   HealthMeasurement act: 0x6fc9ec937c21e4b2dd4ee185477da1d8, exp: 0x6fc9ec937c21e4b2dd4ee185477da1d8