KMAC/MASKED Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.173m	15.138ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.590s	20.731us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.900s	28.386us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.880s	1.175ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.720s	1.821ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.010s	70.100us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.900s	28.386us	20	20	100.00
		kmac_csr_aliasing	9.720s	1.821ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.480s	12.989us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.830s	20.939us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.093h	969.558ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.419m	54.490ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.265m	63.529ms	5	5	100.00
		kmac_test_vectors_sha3_256	27.976m	72.778ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.958m	84.265ms	5	5	100.00
		kmac_test_vectors_sha3_512	25.177m	212.882ms	5	5	100.00
		kmac_test_vectors_shake_128	4.208m	61.253ms	5	5	100.00
		kmac_test_vectors_shake_256	36.548m	323.218ms	5	5	100.00
		kmac_test_vectors_kmac	5.490s	635.935us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.400s	139.823us	5	5	100.00
V2	sideload	kmac_sideload	8.791m	31.172ms	50	50	100.00
V2	app	kmac_app	6.883m	50.837ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.480m	10.816ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.728m	260.843ms	50	50	100.00
V2	error	kmac_error	8.276m	18.522ms	50	50	100.00
V2	key_error	kmac_key_error	19.490s	1.983ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.040s	313.261us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.020s	10.756ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.790s	2.452ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.321m	19.900ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	30.690s	3.982ms	50	50	100.00
V2	stress_all	kmac_stress_all	48.234m	313.506ms	49	50	98.00
V2	intr_test	kmac_intr_test	2.540s	15.595us	50	50	100.00
V2	alert_test	kmac_alert_test	2.480s	104.186us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.630s	307.765us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.630s	307.765us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.590s	20.731us	5	5	100.00
		kmac_csr_rw	2.900s	28.386us	20	20	100.00
		kmac_csr_aliasing	9.720s	1.821ms	5	5	100.00
		kmac_same_csr_outstanding	4.010s	383.535us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.590s	20.731us	5	5	100.00
		kmac_csr_rw	2.900s	28.386us	20	20	100.00
		kmac_csr_aliasing	9.720s	1.821ms	5	5	100.00
		kmac_same_csr_outstanding	4.010s	383.535us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.730s	141.550us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.730s	141.550us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.730s	141.550us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.730s	141.550us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.250s	685.897us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.918m	10.822ms	5	5	100.00
		kmac_tl_intg_err	6.780s	322.033us	18	20	90.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.780s	322.033us	18	20	90.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	30.690s	3.982ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.173m	15.138ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.791m	31.172ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.730s	141.550us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.918m	10.822ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.918m	10.822ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.918m	10.822ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.173m	15.138ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	30.690s	3.982ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.918m	10.822ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.497m	36.250ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.173m	15.138ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.718m	4.313ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			927	940	98.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.34	99.09	94.47	99.89	79.58	97.09	99.37	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 7 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

1.kmac_shadow_reg_errors_with_csr_rw.27145220239169413828345579360721538477793479750260300389487701078780113952028
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @ 103661595 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @ 103661595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.40830118077250552969635512598469313608364056430001369463677097243351177344393
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  14876327 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  14876327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_tl_intg_err has 2 failures.

8.kmac_tl_intg_err.59878636216092054693350071780770203798842989815899067653754390808549825247967
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @ 165626559 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @ 165626559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.kmac_tl_intg_err.29664033118345284082975804628806757022265634715893366789693431256393345783205
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  37129194 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  37129194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.66660098129185033431555265807071591953913681987739319718287059273347482996035
    Line 169, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2653332850 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2653332850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.45998347702734357998064755385673069948085371541887080544755487830421238017422
    Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  43916759 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @  43916759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 35.kmac_stress_all.72595644557693700962712539387013331401200909346234727986199314509766384946386
    Line 456, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/35.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 77895073377 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 77895073377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```