KMAC/UNMASKED Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	59.750s	4.969ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.510s	31.461us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.530s	91.008us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.470s	8.008ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.210s	2.019ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.640s	274.557us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.530s	91.008us	20	20	100.00
		kmac_csr_aliasing	10.210s	2.019ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.260s	30.898us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.950s	134.399us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.306m	247.211ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.425m	33.350ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.553m	64.729ms	5	5	100.00
		kmac_test_vectors_sha3_256	26.503m	76.577ms	5	5	100.00
		kmac_test_vectors_sha3_384	30.890s	6.156ms	5	5	100.00
		kmac_test_vectors_sha3_512	13.236m	96.787ms	5	5	100.00
		kmac_test_vectors_shake_128	32.526m	447.145ms	5	5	100.00
		kmac_test_vectors_shake_256	27.332m	357.267ms	5	5	100.00
		kmac_test_vectors_kmac	4.230s	366.631us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.950s	86.948us	5	5	100.00
V2	sideload	kmac_sideload	6.020m	42.833ms	50	50	100.00
V2	app	kmac_app	4.556m	12.943ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.964m	59.852ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.676m	68.218ms	50	50	100.00
V2	error	kmac_error	7.270m	165.256ms	50	50	100.00
V2	key_error	kmac_key_error	14.550s	3.883ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.943m	10.026ms	41	50	82.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.210s	2.967ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.370s	2.012ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	49.730s	10.311ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.660s	4.372ms	50	50	100.00
V2	stress_all	kmac_stress_all	33.958m	302.071ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.400s	17.050us	50	50	100.00
V2	alert_test	kmac_alert_test	2.350s	90.754us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.570s	551.286us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.570s	551.286us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.510s	31.461us	5	5	100.00
		kmac_csr_rw	2.530s	91.008us	20	20	100.00
		kmac_csr_aliasing	10.210s	2.019ms	5	5	100.00
		kmac_same_csr_outstanding	3.590s	571.861us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.510s	31.461us	5	5	100.00
		kmac_csr_rw	2.530s	91.008us	20	20	100.00
		kmac_csr_aliasing	10.210s	2.019ms	5	5	100.00
		kmac_same_csr_outstanding	3.590s	571.861us	20	20	100.00
V2		TOTAL			731	740	98.78
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.410s	206.131us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.410s	206.131us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.410s	206.131us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.410s	206.131us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.540s	397.490us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.262m	18.744ms	5	5	100.00
		kmac_tl_intg_err	5.670s	713.739us	18	20	90.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.670s	713.739us	18	20	90.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.660s	4.372ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	59.750s	4.969ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.020m	42.833ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.410s	206.131us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.262m	18.744ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.262m	18.744ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.262m	18.744ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	59.750s	4.969ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.660s	4.372ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.262m	18.744ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.731m	98.028ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	59.750s	4.969ms	50	50	100.00
V2S		TOTAL			66	75	88.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.456m	8.649ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			918	940	97.66

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.94	97.17	94.42	100.00	74.38	95.98	99.35	96.27

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 9 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

2.kmac_shadow_reg_errors_with_csr_rw.15600992751836995839738052148370320547858026443426556800484437567660706700096
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  15456221 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  15456221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.114183816957793263569075277217694360084931035211045027455944489181516496577881
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  15457811 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  15457811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 2 failures.

6.kmac_tl_intg_err.108806526316738251289513584339398238505748486866850950764505246932626620219146
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  43772834 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  43772834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_tl_intg_err.82156947657028440155930667714223049434193790769549083028693496360471682211051
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @  10639255 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @  10639255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 0.kmac_stress_all_with_rand_reset.43191577124593393913745057571423821973612149390922928745266119716028505042004
    Line 183, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2603898526 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2603898526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.kmac_stress_all_with_rand_reset.64347708882883926839580302218206994198641075052816439604011466368881579329032
    Line 105, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 459476664 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 459476664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 17.kmac_sideload_invalid.4622919891548039599575441342297968389983381973032852927451289773433927472969
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10020611271 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe943f000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10020611271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.kmac_sideload_invalid.28075637671644784317521698985651771762422880563290255787922966910203144013511
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10025657520 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf78b0000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10025657520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.84981470012727573638904201578766100199061234190650820330176252285571675146711
    Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9061219414 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9061219414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 5.kmac_sideload_invalid.98029502574814410176109138919771454302712783529464303907727583323487122063829
    Line 104, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10267162650 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3fcb6000, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
  UVM_INFO @ 10267162650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 8.kmac_sideload_invalid.9072377388292156557797670942219271171217767301565091253717705210190806551043
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10043208734 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x87c65000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10043208734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 14.kmac_sideload_invalid.56893201642550307591546715592899044955455417337367332923513318716701920765880
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10038297071 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4d36a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10038297071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 15.kmac_sideload_invalid.3161696610062383998635415332501428357783658055460658398310293017910626599925
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/15.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10100762337 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1fdec000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10100762337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 16.kmac_sideload_invalid.109630918198489045537870381126304406335867242232060851528427629082222836217723
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10547205532 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x75b39000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10547205532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 34.kmac_sideload_invalid.100699282903558744204806877120836584544784444783802587743340485708418117280280
    Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10663118836 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdd08d000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
  UVM_INFO @ 10663118836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```