OTBN Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	1.067m	94.653us	1	1	100.00
V1	single_binary	otbn_single	1.667m	523.701us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	27.000s	55.617us	5	5	100.00
V1	csr_rw	otbn_csr_rw	16.000s	12.414us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	39.935us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	35.618us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	57.127us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	16.000s	12.414us	20	20	100.00
		otbn_csr_aliasing	8.000s	35.618us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	709.771us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	38.000s	72.973us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.050m	252.788us	10	10	100.00
V2	multi_error	otbn_multi_err	1.517m	1.234ms	1	1	100.00
V2	back_to_back	otbn_multi	5.350m	1.765ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.133m	254.388us	10	10	100.00
V2	lc_escalation	otbn_escalate	46.000s	38.222us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	45.000s	30.628us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.583m	376.862us	10	10	100.00
V2	alert_test	otbn_alert_test	12.000s	34.244us	50	50	100.00
V2	intr_test	otbn_intr_test	36.000s	29.912us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	46.000s	122.031us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	46.000s	122.031us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	27.000s	55.617us	5	5	100.00
		otbn_csr_rw	16.000s	12.414us	20	20	100.00
		otbn_csr_aliasing	8.000s	35.618us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	15.231us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	27.000s	55.617us	5	5	100.00
		otbn_csr_rw	16.000s	12.414us	20	20	100.00
		otbn_csr_aliasing	8.000s	35.618us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	15.231us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	50.000s	81.180us	10	10	100.00
		otbn_dmem_err	48.000s	60.255us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	48.000s	53.524us	5	5	100.00
		otbn_controller_ispr_rdata_err	48.000s	196.732us	5	5	100.00
		otbn_mac_bignum_acc_err	44.000s	113.537us	5	5	100.00
		otbn_urnd_err	18.000s	15.501us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	44.000s	15.031us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	53.000s	10.002ms	1	2	50.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	34.476us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
		otbn_tl_intg_err	52.000s	319.836us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.350m	300.163us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	1.067m	94.653us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	48.000s	60.255us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	50.000s	81.180us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	52.000s	319.836us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	46.000s	38.222us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	50.000s	81.180us	10	10	100.00
		otbn_dmem_err	48.000s	60.255us	15	15	100.00
		otbn_zero_state_err_urnd	45.000s	30.628us	5	5	100.00
		otbn_illegal_mem_acc	44.000s	15.031us	5	5	100.00
		otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.667m	523.701us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	50.000s	81.180us	10	10	100.00
		otbn_dmem_err	48.000s	60.255us	15	15	100.00
		otbn_zero_state_err_urnd	45.000s	30.628us	5	5	100.00
		otbn_illegal_mem_acc	44.000s	15.031us	5	5	100.00
		otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	46.000s	38.222us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	50.000s	81.180us	10	10	100.00
		otbn_dmem_err	48.000s	60.255us	15	15	100.00
		otbn_zero_state_err_urnd	45.000s	30.628us	5	5	100.00
		otbn_illegal_mem_acc	44.000s	15.031us	5	5	100.00
		otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.667m	523.701us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	24.000s	22.825us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	33.000s	37.664us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	6.767m	2.905ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	6.767m	2.905ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	45.000s	24.114us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	47.000s	182.262us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	20.722us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	20.722us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	16.000s	35.381us	3	7	42.86
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.667m	523.701us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.667m	523.701us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.667m	523.701us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	5.350m	1.765ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.667m	523.701us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.667m	523.701us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	33.000s	96.396us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.667m	523.701us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.117m	1.127ms	2	5	40.00
V2S		TOTAL			151	163	92.64
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.900m	3.460ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			567	585	96.92

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.04	99.63	95.86	99.71	92.92	93.60	97.44	91.01	100.00

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 4 failures.

2.otbn_sec_wipe_err.18735991437698509154329761462797917627394471721351891189028841443841774256062
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18231012 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  18231012 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  18231012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.96184698094911241415960718305976457618684622067935914037278223191867702351011
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18945148 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  18945148 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  18945148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.69575972018899138901471250351826800530944395854500235718287043361659688964040
Line 128, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 138159133 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 138159133 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 138159133 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 138159133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_cm.106817418892853297158070785431923583386394009808945154786705545052388580291403
Line 86, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 8279691 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 8279691 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @   8279691 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @   8279691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 2.otbn_stress_all_with_rand_reset.820293555571703092918124473033857193675755598577041982319203034371327622953
    Line 351, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 886054030 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 886054030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.otbn_stress_all_with_rand_reset.76646723998236285126800440643567963780127570306140422707097612985525507069201
    Line 391, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1193245243 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1193245243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.1055425423056172460252610883979242865012198030779228353025978998896646174995
    Line 374, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3459699029 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 3459699029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.otbn_stress_all_with_rand_reset.82976348282455429135736169704222643091638431229198536025203284259684596856475
    Line 140, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  13662262 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  13662262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:

Test otbn_passthru_mem_tl_intg_err has 2 failures.

3.otbn_passthru_mem_tl_intg_err.37698144569167976652276811751213778690629841044573421112317304574977988084408
Line 92, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  28596756 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  28596756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.otbn_passthru_mem_tl_intg_err.91937722318822228540973775588610576172203065050249084707583546703776225135506
Line 92, in log /nightly/runs/scratch/master/otbn-sim-xcelium/16.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  69912895 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  69912895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred! has 1 failures:
- Test otbn_mem_gnt_acc_err has 1 failures.
  - 0.otbn_mem_gnt_acc_err.91093122591843925382367258943400755519053895784856937165588523344008443128405
    Line 106, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/run.log
```
  UVM_FATAL @ 10001979541 ps: (otbn_mem_gnt_acc_err_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.otbn_mem_gnt_acc_err_vseq] timeout occurred!
  UVM_INFO @ 10001979541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 0.otbn_partial_wipe.38994345846243250683887358016342539032324193623267988693587481553756237765271
    Line 102, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 10000009 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  10000009 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  10000009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.106164226308620773014071096229081414737523016892684597433023614668817539552087
    Line 258, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1468813279 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1468813279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 5.otbn_passthru_mem_tl_intg_err.99454554578670734731557093929517839500378050219373747791076039220932470429043
    Line 92, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  16771555 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  16771555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```