4c0a27d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 9.000s | 495.028us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 28.063us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 5.000s | 20.850us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 7.000s | 217.241us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 54.490us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 57.205us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 20.850us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 54.490us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 49.467m | 600.000ms | 23 | 50 | 46.00 |
| V2 | cnt_rollover | cnt_rollover | 1.100m | 37.439ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 6.000s | 92.912us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.889h | 1.428s | 17 | 50 | 34.00 |
| V2 | alert_test | pattgen_alert_test | 5.000s | 20.951us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 15.965us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 6.000s | 280.104us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 6.000s | 280.104us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 28.063us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 20.850us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 54.490us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 31.665us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 28.063us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 20.850us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 54.490us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 31.665us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 280 | 340 | 82.35 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 6.000s | 466.583us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 5.000s | 62.334us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 6.000s | 466.583us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.783m | 6.593ms | 1 | 50 | 2.00 |
| V3 | TOTAL | 1 | 50 | 2.00 | |||
| Unmapped tests | pattgen_inactive_level | 5.217m | 10.011ms | 32 | 50 | 64.00 | |
| TOTAL | 443 | 570 | 77.72 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.72 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 88.15 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:
0.pattgen_stress_all_with_rand_reset.76738460779642859660101856103260820446827860431605611175972862846404039660264
Line 144, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3913461359 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3913497816 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3913497816 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 3913777816 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.84400720705544410706157722468132275619409746461373768878449574810974222821548
Line 115, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1828507947 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1828512455 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1828512455 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1828706901 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 46 more failures.
Job timed out after * minutes has 23 failures:
0.pattgen_perf.55399125201786161782016526822932651739868280205497235128812305336162113834632
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Job timed out after 60 minutes
2.pattgen_perf.44758525785694919175675915091125189768902268892939128289238195234553185389116
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 8 more failures.
1.pattgen_stress_all.66349860812131554347756483391420514625331598458227494123664069429492535339474
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
3.pattgen_stress_all.25330246329006809699233306615797083005351444564234677706000906621189726378881
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 11 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 20 failures:
6.pattgen_stress_all.82423311908508351598618846636203940876359020647349172017418226135378287840456
Line 142, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log
UVM_ERROR @ 525357194 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10178
11.pattgen_stress_all.13047774829544499592082116394515851519636239262610499173375534330840069143150
Line 122, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log
UVM_ERROR @ 77128579 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10310
... and 18 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 17 failures:
1.pattgen_perf.87832882541328736362176612999149343614894709481380880557218839434963641864802
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pattgen_perf.33842992378209449164341411680389783591769295450822517597455957781755181461294
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 2 failures:
0.pattgen_inactive_level.2044560687004583139265431336453138630815072869953942185131917206371044893046
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10026670531 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x1962a9d0, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10026670531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.pattgen_inactive_level.25166110154570911655395485834066160813164785296658172080060148807727021770254
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10158798127 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x3d20890, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10158798127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
10.pattgen_inactive_level.34839766124730853090007412580040104739769041412176433275680328760659499476798
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10104024469 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x175bfd10, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10104024469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.pattgen_inactive_level.61143400445659086466259089651219813571375097195243871628894193814765017793886
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10024650329 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3d48c690, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10024650329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
27.pattgen_inactive_level.79044976716691188781699103271636793422992420097738828574723926273077199322628
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025255043 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5d150b90, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10025255043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.pattgen_inactive_level.64462564364190260154208193494651890341329457678391202940839986340256128526850
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010852947 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2df47310, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10010852947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
34.pattgen_inactive_level.40953694042361437737714571266123839978620351521352445170343631297239646732211
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012406098 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x22ec64d0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10012406098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.pattgen_inactive_level.72995011507384081115752420894824963228339052358488726753887723563419319591619
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10041079875 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8b5eac90, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10041079875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
2.pattgen_inactive_level.92032542919990549792272566924515498863307420120647406870536399275747025648816
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10023195209 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x98f48ed0, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10023195209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) has 1 failures:
9.pattgen_inactive_level.69982142427288594654044937914091727877052115539849523884724463085518851000987
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10190690834 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xef2050, Comparison=CompareOpEq, exp_data=0x0, call_count=28)
UVM_INFO @ 10190690834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
11.pattgen_inactive_level.62510252845561460308663085824843309905003857370916752707266123761456754297390
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010759458 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x75cd5610, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10010759458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
18.pattgen_inactive_level.71163922046757502690738194516987554821736766789269849857376207990588044791659
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10027254112 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xea97d890, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10027254112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
26.pattgen_inactive_level.88886584660329276067158047995384193141044582386615649786603440266110797242886
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10031200163 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xea693110, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10031200163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
33.pattgen_inactive_level.74878677386501791416193465037648024114065964604227404549554491128562342561692
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10338557885 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x9135f10, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10338557885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
33.pattgen_stress_all_with_rand_reset.46228849537601545066495032233122974536093853380026795421944300006302176615752
Line 126, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 186346699 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
39.pattgen_inactive_level.6993736253927118609762301446866470211755021054635411711691582764791799077647
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10008404177 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x25c95f10, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10008404177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
44.pattgen_inactive_level.65777431825328751737006110320393442884696854897826576150252884151906943071779
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10003720845 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb322f710, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10003720845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
45.pattgen_inactive_level.8270466640717140091355146145634589794780286246724238484805286762523486537173
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10330726229 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x4c09b890, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 10330726229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
47.pattgen_inactive_level.73809852598483700028608436327723831704782215259462136071956672019542188646181
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10047775968 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x92af2a10, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10047775968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---