ROM_CTRL/32KB Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.530s	1.409ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.900s	176.136us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.430s	579.960us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.340s	128.918us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.620s	127.847us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.660s	188.171us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.430s	579.960us	20	20	100.00
		rom_ctrl_csr_aliasing	7.620s	127.847us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.490s	130.650us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.850s	581.092us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.440s	574.202us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	28.450s	611.726us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.430s	1.088ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.030s	167.264us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.460s	280.347us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.460s	280.347us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.900s	176.136us	5	5	100.00
		rom_ctrl_csr_rw	7.430s	579.960us	20	20	100.00
		rom_ctrl_csr_aliasing	7.620s	127.847us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.440s	598.384us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.900s	176.136us	5	5	100.00
		rom_ctrl_csr_rw	7.430s	579.960us	20	20	100.00
		rom_ctrl_csr_aliasing	7.620s	127.847us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.440s	598.384us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	26.950s	3.317ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.157m	762.279us	5	5	100.00
		rom_ctrl_tl_intg_err	54.010s	431.464us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.157m	762.279us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.157m	762.279us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.157m	762.279us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.157m	762.279us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.530s	1.409ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.530s	1.409ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.530s	1.409ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	54.010s	431.464us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
		rom_ctrl_kmac_err_chk	8.430s	1.088ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.312m	90.584ms	18	20	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	26.950s	3.317ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.157m	762.279us	5	5	100.00
V2S		TOTAL			63	65	96.92
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.325m	19.759ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			264	266	99.25

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	100.00	99.41	100.00	100.00	100.00	98.97	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.48410156807731145074852419322892015375123970838059247687267670634869645789587
      Line 82, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 349414786 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 349414786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 9.rom_ctrl_corrupt_sig_fatal_chk.13554103020606241528716750455495671846956585545843043862777452200841671104787
      Line 93, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1595708805 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1595708805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---