ROM_CTRL/64KB Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	11.960s	307.166us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	13.820s	306.835us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	12.140s	303.078us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.630s	1.307ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.490s	208.632us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.320s	309.865us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	12.140s	303.078us	20	20	100.00
		rom_ctrl_csr_aliasing	10.490s	208.632us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.310s	4.176ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.920s	1.027ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	14.830s	306.221us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	46.110s	1.461ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	20.280s	547.909us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	17.020s	2.008ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.550s	208.397us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.550s	208.397us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	13.820s	306.835us	5	5	100.00
		rom_ctrl_csr_rw	12.140s	303.078us	20	20	100.00
		rom_ctrl_csr_aliasing	10.490s	208.632us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.250s	1.087ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	13.820s	306.835us	5	5	100.00
		rom_ctrl_csr_rw	12.140s	303.078us	20	20	100.00
		rom_ctrl_csr_aliasing	10.490s	208.632us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.250s	1.087ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.037m	3.147ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	7.480m	817.854us	5	5	100.00
		rom_ctrl_tl_intg_err	2.228m	937.051us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	7.480m	817.854us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	7.480m	817.854us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	7.480m	817.854us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	7.480m	817.854us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	11.960s	307.166us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	11.960s	307.166us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	11.960s	307.166us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.228m	937.051us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
		rom_ctrl_kmac_err_chk	20.280s	547.909us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.292m	79.714ms	19	20	95.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.037m	3.147ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	7.480m	817.854us	5	5	100.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.797m	59.805ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			265	266	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	100.00	99.41	100.00	100.00	100.00	98.97	99.28

Failure Buckets

• Offending '(counter_lnt -> kmac_rom_vld_o)' has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.66399618081071864733419728732754893356140753614943134282349255239537768668275
      Line 85, in log /nightly/runs/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

            Offending '(counter_lnt -> kmac_rom_vld_o)'
        UVM_ERROR @ 1192948323 ps: (rom_ctrl_fsm.sv:317) [ASSERT FAILED] CounterLntImpliesKmacRomVldO_A
        UVM_INFO @ 1192948323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---