RV_TIMER Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.100s	39.424us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.250s	22.754us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.090s	81.611us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.030s	280.189us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.990s	168.097us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.360s	25.044us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.090s	81.611us	20	20	100.00
		rv_timer_csr_aliasing	1.990s	168.097us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	13.560s	7.953ms	20	20	100.00
V2	disabled	rv_timer_disabled	5.430s	1.975ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	19.017m	3.900s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	19.017m	3.900s	10	10	100.00
V2	stress	rv_timer_stress_all	10.180s	5.185ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.260s	13.919us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.290s	16.630us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.900s	789.381us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.900s	789.381us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.250s	22.754us	5	5	100.00
		rv_timer_csr_rw	2.090s	81.611us	20	20	100.00
		rv_timer_csr_aliasing	1.990s	168.097us	5	5	100.00
		rv_timer_same_csr_outstanding	2.130s	65.179us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.250s	22.754us	5	5	100.00
		rv_timer_csr_rw	2.090s	81.611us	20	20	100.00
		rv_timer_csr_aliasing	1.990s	168.097us	5	5	100.00
		rv_timer_same_csr_outstanding	2.130s	65.179us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.540s	78.172us	5	5	100.00
		rv_timer_tl_intg_err	2.820s	272.346us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.820s	272.346us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	55.700s	8.738ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	1.790s	68.264us	10	10	100.00
		rv_timer_max	2.010s	114.347us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00