SPI_DEVICE/1R1W Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.312m	150.682ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.940s	48.413us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.360s	469.634us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.400s	2.344ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.980s	1.003ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.530s	104.149us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.360s	469.634us	20	20	100.00
		spi_device_csr_aliasing	20.980s	1.003ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.270s	17.312us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.260s	40.818us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.440s	23.543us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.340s	1.711us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.370s	4.323us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	13.580s	282.803us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.580s	282.803us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.390s	7.996ms	50	50	100.00
		spi_device_tpm_sts_read	2.750s	235.649us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.330s	40.744ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.720s	116.197ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.370s	17.550ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.370s	17.550ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	40.190s	3.829ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	40.190s	3.829ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	40.190s	3.829ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	40.190s	3.829ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	40.190s	3.829ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	53.720s	102.661ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.898m	104.860ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.898m	104.860ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.898m	104.860ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.107m	9.421ms	50	50	100.00
		spi_device_read_buffer_direct	21.740s	3.538ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.898m	104.860ms	50	50	100.00
		spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.410m	149.954ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.530s	2.074ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.530s	2.074ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.312m	150.682ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.411m	296.221ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.107m	424.463ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.420s	26.721us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.430s	14.507us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.100s	833.513us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.100s	833.513us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.940s	48.413us	5	5	100.00
		spi_device_csr_rw	4.360s	469.634us	20	20	100.00
		spi_device_csr_aliasing	20.980s	1.003ms	5	5	100.00
		spi_device_same_csr_outstanding	5.870s	617.474us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.940s	48.413us	5	5	100.00
		spi_device_csr_rw	4.360s	469.634us	20	20	100.00
		spi_device_csr_aliasing	20.980s	1.003ms	5	5	100.00
		spi_device_same_csr_outstanding	5.870s	617.474us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.890s	431.094us	5	5	100.00
		spi_device_tl_intg_err	25.000s	1.095ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.000s	1.095ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.511m	52.526ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	98.99	96.55	83.54	89.36	98.41	95.66	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.24764906230357111550068456575966361177410870400926827736166474146070392723961
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4145669 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[67])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4145669 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4145669 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[963])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.78828684612266976993519086016821595712235569085545165425883936505832857035050
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2201100 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[9])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2201100 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2201100 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[905])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.30853932451080792694588656761796648560072727229619191541323814673204503122195
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1920037 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd18d9f [110100011000110110011111] vs 0x0 [0])
        UVM_ERROR @   1949037 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb4f657 [101101001111011001010111] vs 0x0 [0])
        UVM_ERROR @   2028037 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb45660 [101101000101011001100000] vs 0x0 [0])
        UVM_ERROR @   2116037 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe50ef9 [111001010000111011111001] vs 0x0 [0])
        UVM_ERROR @   2195037 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdc4cc [11011100010011001100] vs 0x0 [0])