SPI_HOST Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	3.033m	200.000ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	26.584us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	30.378us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	233.727us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	26.937us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	26.535us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	30.378us	20	20	100.00
		spi_host_csr_aliasing	4.000s	26.937us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	18.028us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	18.305us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	43.000s	66.441us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	47.000s	5.394ms	50	50	100.00
		spi_host_error_cmd	43.000s	20.148us	50	50	100.00
		spi_host_event	1.283m	1.292ms	50	50	100.00
V2	clock_rate	spi_host_speed	43.000s	27.313us	50	50	100.00
V2	speed	spi_host_speed	43.000s	27.313us	50	50	100.00
V2	chip_select_timing	spi_host_speed	43.000s	27.313us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	46.000s	266.343us	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	43.000s	93.888us	50	50	100.00
V2	cpol_cpha	spi_host_speed	43.000s	27.313us	50	50	100.00
V2	full_cycle	spi_host_speed	43.000s	27.313us	50	50	100.00
V2	duplex	spi_host_smoke	3.033m	200.000ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	3.033m	200.000ms	49	50	98.00
V2	stress_all	spi_host_stress_all	2.067m	8.244ms	50	50	100.00
V2	spien	spi_host_spien	3.933m	7.064ms	50	50	100.00
V2	stall	spi_host_status_stall	11.483m	44.394ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	43.000s	49.799us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	47.000s	5.394ms	50	50	100.00
V2	alert_test	spi_host_alert_test	41.000s	27.342us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	46.485us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	53.428us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	53.428us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	26.584us	5	5	100.00
		spi_host_csr_rw	5.000s	30.378us	20	20	100.00
		spi_host_csr_aliasing	4.000s	26.937us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	19.985us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	26.584us	5	5	100.00
		spi_host_csr_rw	5.000s	30.378us	20	20	100.00
		spi_host_csr_aliasing	4.000s	26.937us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	19.985us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	95.461us	20	20	100.00
		spi_host_sec_cm	41.000s	216.734us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	95.461us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	9.617m	14.998ms	10	10	100.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.26	96.78	93.27	98.69	94.36	88.02	100.00	97.27	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_smoke has 1 failures.
  - 9.spi_host_smoke.38400581188630974173035254288466710329391329540955524955446689009758212097940
    Line 126, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

45.spi_host_status_stall.77174443798250993505479880737042836010622959135105925971095749175974372432651
Line 3676, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 6241842650 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 6241842650 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=6241843000 ps
  UVM_INFO @ 6241842650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---