SRAM_CTRL/MAIN Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.397m	2.261ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.100s	37.310us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.230s	40.165us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.590s	122.957us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.150s	34.884us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.290s	1.476ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.230s	40.165us	20	20	100.00
		sram_ctrl_csr_aliasing	2.150s	34.884us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.134m	17.979ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.131m	20.082ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	24.996m	48.838ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.909m	6.730ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	42.056m	323.590ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.511m	335.909ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.959m	18.338ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.967m	120.049ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.756m	2.517ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.959m	483.004ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.707m	3.616ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.708m	1.601ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.627m	1.773ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.593m	8.562ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.850s	4.799ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.935h	1.221s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.250s	28.599us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.700s	649.424us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.700s	649.424us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.100s	37.310us	5	5	100.00
		sram_ctrl_csr_rw	2.230s	40.165us	20	20	100.00
		sram_ctrl_csr_aliasing	2.150s	34.884us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.270s	36.630us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.100s	37.310us	5	5	100.00
		sram_ctrl_csr_rw	2.230s	40.165us	20	20	100.00
		sram_ctrl_csr_aliasing	2.150s	34.884us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.270s	36.630us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.070m	7.312ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.150s	4.978us	0	5	0.00
		sram_ctrl_tl_intg_err	4.360s	287.780us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.150s	4.978us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.360s	287.780us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.593m	8.562ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	26.593m	8.562ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.230s	40.165us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.967m	120.049ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.967m	120.049ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.967m	120.049ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.959m	18.338ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	14.260s	9.388ms	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.070m	7.312ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	15.310s	13.162ms	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.397m	2.261ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.397m	2.261ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.967m	120.049ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.150s	4.978us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.959m	18.338ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.150s	4.978us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.150s	4.978us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.397m	2.261ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.150s	4.978us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.444m	13.812ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1168	1190	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.29	93.01	85.18	100.00	98.03	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 0.sram_ctrl_readback_err.110793811741929988210322128575168156484368406661211693908907131551074337710607
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 5976203942 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x6f) != exp (0x32)
        UVM_INFO @ 5976203942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_readback_err.54648612834115319245676911383420045837274699165678126651021809301198095931873
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1368468089 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1e) != exp (0xf)
        UVM_INFO @ 1368468089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 7 failures:

  • Test sram_ctrl_mubi_enc_err has 7 failures.

    • 5.sram_ctrl_mubi_enc_err.20631357161910514082878915370372364113583665889185194315720732884135444606980
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1030614003 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1030614003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.sram_ctrl_mubi_enc_err.62877388948775604996096481949263318980914953001392684651368809713052695679086
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 9388430868 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 9388430868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 2.sram_ctrl_sec_cm.34766233064871268050100580446929924700857120027512809546632243090953812975143
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4978189 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4978189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.49226395214805993124409138748473977068775496103480660077044737851431776668448
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7035361 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7035361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.37070817235699882686927909247926715851457883044367341585547434440744220898315
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1083693 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1083693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.37257287667502367046571188097876919792637402104433044424483503596063674139766
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @    861287 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @    861287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.35710533799607043135101164579415058798787700708319433266281710996716056541310
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4016165 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4016165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---