SRAM_CTRL/RET Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.650m	1.416ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.080s	76.038us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.240s	47.636us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.610s	471.078us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.070s	21.128us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.580s	667.468us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.240s	47.636us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	21.128us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.440s	3.092ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.950s	803.996us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	22.442m	31.104ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.222m	53.031ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.415m	4.833ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.511m	4.915ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.250s	1.140ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.378m	19.578ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.517m	5.587ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.068m	98.118ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.472m	532.008us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.527m	251.694us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.703m	569.265us	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.015m	23.687ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.020s	83.569us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.056h	17.465ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	3.990s	186.483us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.350s	660.256us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.350s	660.256us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.080s	76.038us	5	5	100.00
		sram_ctrl_csr_rw	2.240s	47.636us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	21.128us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.230s	27.363us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.080s	76.038us	5	5	100.00
		sram_ctrl_csr_rw	2.240s	47.636us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	21.128us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.230s	27.363us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.520s	817.942us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.770s	3.932us	0	5	0.00
		sram_ctrl_tl_intg_err	4.380s	691.940us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.770s	3.932us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.380s	691.940us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.015m	23.687ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.015m	23.687ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.240s	47.636us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.378m	19.578ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.378m	19.578ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.378m	19.578ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.250s	1.140ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.060s	40.282us	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.520s	817.942us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.150s	35.695us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.650m	1.416ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.650m	1.416ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.378m	19.578ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.770s	3.932us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.250s	1.140ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.770s	3.932us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.770s	3.932us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.650m	1.416ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.770s	3.932us	0	5	0.00
V2S		TOTAL			125	145	86.21
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.801m	11.371ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1169	1190	98.24

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.26	93.01	85.10	100.00	97.99	98.58	98.52

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 4.sram_ctrl_readback_err.22989699317602937483611943563329359438471374293575756523815594947230207394916
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 180889243 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x3c) != exp (0x58)
        UVM_INFO @ 180889243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.sram_ctrl_readback_err.105272678915602929766150967905980930213782477649021753482652344886739964016593
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/12.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  44558386 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x5a) != exp (0x5d)
        UVM_INFO @  44558386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 12.sram_ctrl_mubi_enc_err.43120244524182426276224226464660675847075839218992147757070673871546515478053
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  96327528 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  96327528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 16.sram_ctrl_mubi_enc_err.22490525781422570181184530064233125398941681602499804635677490661842650436344
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 117259582 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 117259582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.32026147004483822683682456415450939496110700680668371454407338288682345066078
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3932436 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3932436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.16301974715168392444661894099528029235290353552200676316535585831984106385266
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6446434 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6446434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.112594109624822765453922157999196881524180636040525560884682510229708406203609
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2882746 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2882746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 10.sram_ctrl_csr_mem_rw_with_rand_reset.93141539707064162645830600522452658015112201457962808309628105591575162871699
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 152845412 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @ 152845412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---