SYSRST_CTRL Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: `4c0a27d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	10.160s	2.110ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	10.500s	2.460ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.900s	2.147ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.430s	2.367ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.900s	4.017ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	10.700s	2.060ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.748m	74.183ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	15.870s	2.806ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	10.850s	2.062ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	10.700s	2.060ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	15.870s	2.806ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	6.717m	156.251ms	49	50	98.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.149m	153.909ms	94	100	94.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	22.908m	568.207ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	8.545m	254.726ms	46	50	92.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	11.450s	2.508ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	10.280s	2.209ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	14.208m	690.545ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	12.410s	2.615ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	3.674m	2.658s	43	50	86.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.034m	30.092ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	23.282m	942.731ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	9.920s	2.009ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	10.170s	2.011ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	11.380s	2.132ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	11.380s	2.132ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.900s	4.017ms	5	5	100.00
		sysrst_ctrl_csr_rw	10.700s	2.060ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	15.870s	2.806ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	32.210s	10.761ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.900s	4.017ms	5	5	100.00
		sysrst_ctrl_csr_rw	10.700s	2.060ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	15.870s	2.806ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	32.210s	10.761ms	20	20	100.00
V2		TOTAL			673	692	97.25
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.042m	22.017ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	53.580s	22.204ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	53.580s	22.204ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	30.140s	7.321ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			911	932	97.75

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.00	99.28	97.60	100.00	95.51	99.52	99.33	87.75

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:

Test sysrst_ctrl_edge_detect has 3 failures.

2.sysrst_ctrl_edge_detect.46068152984819086922489290889656543439080854824980644493908376918399645186045
Line 386, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 3795120878 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 3795150877 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 3795150877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.sysrst_ctrl_edge_detect.98108183644286752403540115774330924113081991108024677213347852884351330846887
Line 384, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 2825096775 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 2825207885 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 2825207885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test sysrst_ctrl_ultra_low_pwr has 3 failures.

19.sysrst_ctrl_ultra_low_pwr.16494793714024171383592740880274875215657954777359113774084024575144920551529
Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 4760981181 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 4761096566 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 4761096566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sysrst_ctrl_ultra_low_pwr.75953894595584422847796415895610167589041214699144577242215366058972929058664
Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3089070999 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 3089130998 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 3089130998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test sysrst_ctrl_stress_all has 1 failures.

33.sysrst_ctrl_stress_all.84265568578634115189545981323663197241668826705230053871273415884058918627438
Line 386, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 10412480698 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 10412611131 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 10412611131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 3 failures:

Test sysrst_ctrl_ultra_low_pwr has 3 failures.

18.sysrst_ctrl_ultra_low_pwr.40425649783303735128791651292943103869529613966597345595689379431575394326542
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2112422775 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 4279922775 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4279922775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.sysrst_ctrl_ultra_low_pwr.44603566922344150291941975324335840375135938470596304643614762447901689205285
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2183698822 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2211198822 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 2836198822 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 2889609806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

22.sysrst_ctrl_combo_detect_with_pre_cond.99586720681004895410447523275435194686859021329260517731439507753996355948127
Line 411, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 36524005991 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 37589005991 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 37609005991 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 47781446663 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0xee
  UVM_INFO @ 47781520345 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2b

78.sysrst_ctrl_combo_detect_with_pre_cond.82446175793944591225882983021118266845709229177848099594363437987554957920010
Line 452, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 90983669938 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 90983669938 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 90983669938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

4.sysrst_ctrl_stress_all_with_rand_reset.39581272306596269687272742643702182656224104728295470046812428554085073276163
Line 402, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7917260999 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 7917260999 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7917260999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

11.sysrst_ctrl_stress_all_with_rand_reset.96196124156029268787346437848126302622628874785792560676544042398701730992682
Line 391, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4335993806 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4338632874 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 2/5
  UVM_INFO @ 4341564248 ps: (cip_base_vseq.sv:787) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 3/5
  UVM_INFO @ 4341564248 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/612

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

13.sysrst_ctrl_combo_detect_with_pre_cond.96540294878727288860848388347974561389054903766805291394414909589967579055502
Line 482, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 97583705603 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 97738705603 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 97758705603 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 97798832963 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
  UVM_INFO @ 97798832963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:239) [sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect has 1 failures.

19.sysrst_ctrl_combo_detect.23980213557575652830573804651081480764455108739919294531914200559928943793450
Line 385, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest/run.log

  UVM_ERROR @ 17009171477 ps: (sysrst_ctrl_combo_detect_vseq.sv:239) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
  UVM_ERROR @ 17009171477 ps: (cip_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 17009171477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

20.sysrst_ctrl_combo_detect_with_pre_cond.84572152485431828675206483853162150315808619228132995475598462082723937377856
Line 398, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 35326401203 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4
  UVM_ERROR @ 35326401203 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 35326401203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:580) [sysrst_ctrl_edge_detect_vseq] timeout occurred! has 1 failures:
- Test sysrst_ctrl_edge_detect has 1 failures.
  - 24.sysrst_ctrl_edge_detect.27015780115668015617873079562368796138501309059238542048387147659179954446786
    Line 382, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest/run.log
```
  UVM_FATAL @ 12775116721 ps: (cip_base_vseq.sv:580) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] timeout occurred!
  UVM_INFO @ 12775116721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:580) [sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred! has 1 failures:
- Test sysrst_ctrl_ultra_low_pwr has 1 failures.
  - 47.sysrst_ctrl_ultra_low_pwr.55620846329893975815320583632359174846773386238771771077442077220787952128470
    Line 382, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest/run.log
```
  UVM_FATAL @ 17282897228 ps: (cip_base_vseq.sv:580) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred!
  UVM_INFO @ 17282897228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

63.sysrst_ctrl_combo_detect_with_pre_cond.66880523674108234523366752542641631778086247582369326173835332081855357598815
Line 389, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 12863163486 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-4
  UVM_ERROR @ 12863163486 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4
  UVM_INFO @ 12863163486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

89.sysrst_ctrl_combo_detect_with_pre_cond.71667865480932815795497669633575271822481565167888684357120999439782435684984
Line 430, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 62712274909 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 62712274909 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 62712274909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---