UART Simulation Results

Sunday May 11 2025 00:08:57 UTC

GitHub Revision: 4c0a27d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.319m	11.636ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.320s	63.808us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.380s	50.057us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.350s	60.231us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.310s	24.398us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.560s	105.370us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.380s	50.057us	20	20	100.00
		uart_csr_aliasing	2.310s	24.398us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.048m	142.889ms	50	50	100.00
V2	parity	uart_smoke	1.319m	11.636ms	50	50	100.00
		uart_tx_rx	6.048m	142.889ms	50	50	100.00
V2	parity_error	uart_intr	7.650m	323.571ms	50	50	100.00
		uart_rx_parity_err	8.832m	163.784ms	50	50	100.00
V2	watermark	uart_tx_rx	6.048m	142.889ms	50	50	100.00
		uart_intr	7.650m	323.571ms	50	50	100.00
V2	fifo_full	uart_fifo_full	11.632m	299.406ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.862m	120.634ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.435m	111.155ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.650m	323.571ms	50	50	100.00
V2	rx_break_err	uart_intr	7.650m	323.571ms	50	50	100.00
V2	rx_timeout	uart_intr	7.650m	323.571ms	50	50	100.00
V2	perf	uart_perf	21.945m	25.005ms	50	50	100.00
V2	sys_loopback	uart_loopback	26.780s	11.299ms	50	50	100.00
V2	line_loopback	uart_loopback	26.780s	11.299ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.575m	124.250ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.323m	65.519ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	33.660s	6.488ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.053m	6.076ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.846m	132.956ms	50	50	100.00
V2	stress_all	uart_stress_all	27.689m	448.559ms	50	50	100.00
V2	alert_test	uart_alert_test	2.200s	23.845us	50	50	100.00
V2	intr_test	uart_intr_test	2.380s	25.886us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.680s	699.975us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.680s	699.975us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.320s	63.808us	5	5	100.00
		uart_csr_rw	2.380s	50.057us	20	20	100.00
		uart_csr_aliasing	2.310s	24.398us	5	5	100.00
		uart_same_csr_outstanding	2.420s	29.268us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.320s	63.808us	5	5	100.00
		uart_csr_rw	2.380s	50.057us	20	20	100.00
		uart_csr_aliasing	2.310s	24.398us	5	5	100.00
		uart_same_csr_outstanding	2.420s	29.268us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	2.370s	65.433us	5	5	100.00
		uart_tl_intg_err	2.970s	1.782ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.970s	1.782ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.825m	3.391ms	95	100	95.00
V3		TOTAL			95	100	95.00
		TOTAL			1315	1320	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.17	98.25	91.55	--	98.14	100.00	99.55

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:

  • Test uart_stress_all_with_rand_reset has 3 failures.

    • 31.uart_stress_all_with_rand_reset.75958380024007567061330555922972398476269714498354662485049027819130101688571
      Line 112, in log /nightly/runs/scratch/master/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1802909100 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1802914896 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1802914896 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 2/5
        UVM_INFO @ 1802919409 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
      

    • 55.uart_stress_all_with_rand_reset.83253722429876682638295339539271137383968533030469271158344182553272949183144
      Line 74, in log /nightly/runs/scratch/master/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 186130042 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 186130677 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 186130677 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 186146991 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 70.uart_stress_all_with_rand_reset.58386345942592605434314290921478999399264655540596164870708918329213658116431
      Line 121, in log /nightly/runs/scratch/master/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14015205342 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 14015205342 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 4/10
        UVM_INFO @ 14016372011 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 4/10
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 78.uart_stress_all_with_rand_reset.1620724345678715352837621862990802176435868759612608819307343108589192475012
      Line 178, in log /nightly/runs/scratch/master/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4213115951 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 4236097356 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 8/10
        UVM_INFO @ 4236164772 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 8/10