ADC_CTRL Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: `54711bc`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.760s	5.841ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	6.320s	1.366ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.160s	521.199us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.337m	42.749ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.840s	559.043us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.420s	568.855us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.160s	521.199us	20	20	100.00
		adc_ctrl_csr_aliasing	4.840s	559.043us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.971m	493.753ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.401m	494.007ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.114m	502.038ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	21.805m	488.522ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.206m	564.843ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.236m	595.270ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.788m	520.065ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	21.367m	510.829ms	31	50	62.00
V2	poweron_counter	adc_ctrl_poweron_counter	20.600s	5.004ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.585m	45.083ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	5.101m	116.519ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	55.397m	1.493s	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	3.880s	530.310us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	4.040s	534.304us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.880s	562.222us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.880s	562.222us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	6.320s	1.366ms	5	5	100.00
		adc_ctrl_csr_rw	4.160s	521.199us	20	20	100.00
		adc_ctrl_csr_aliasing	4.840s	559.043us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.830s	4.965ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	6.320s	1.366ms	5	5	100.00
		adc_ctrl_csr_rw	4.160s	521.199us	20	20	100.00
		adc_ctrl_csr_aliasing	4.840s	559.043us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.830s	4.965ms	20	20	100.00
V2		TOTAL			716	740	96.76
V2S	tl_intg_err	adc_ctrl_sec_cm	28.040s	8.359ms	5	5	100.00
		adc_ctrl_tl_intg_err	24.730s	8.555ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	24.730s	8.555ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.389m	10.000s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			894	920	97.17

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	99.11	96.45	100.00	100.00	99.01	98.06	90.48

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 16 failures:

Test adc_ctrl_clock_gating has 13 failures.

1.adc_ctrl_clock_gating.5206754118805524408413253789364915576258026316538874538523288856303536738924
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.adc_ctrl_clock_gating.92112253019278588944378359584413896000776323729204223553027158548913040831520
Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 7.adc_ctrl_stress_all_with_rand_reset.14382072095567597593354011794251230240567961695633157837762145781199611725728
  Line 152, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test adc_ctrl_stress_all has 2 failures.

14.adc_ctrl_stress_all.55699676661871866404559240482934768911620380482399319638557691691102234407505
Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.adc_ctrl_stress_all.63616026469251161182186590097587637652823615946038740862723887819876135680431
Line 183, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 6 failures:

Test adc_ctrl_clock_gating has 4 failures.

4.adc_ctrl_clock_gating.59036236387790625417701928306370574918984919817417237995767702475370957669771
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 3487887037 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 3487887037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.adc_ctrl_clock_gating.46955397351378798126693216721900444995699132438892855300921519946219123301706
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 3729617959 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 3729617959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all has 1 failures.

22.adc_ctrl_stress_all.107270612090183860043251894198464659613431738528082334654005115202554211439695
Line 179, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 229947084926 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 229947084926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 49.adc_ctrl_stress_all_with_rand_reset.18179205655436155421879082404714614451269227608168704542594882551432714889645
  Line 289, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63277130160 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 63277130160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_clock_gating has 2 failures.

0.adc_ctrl_clock_gating.107498668728988221837756612322674721443473128650454932967399392918726574814682
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 88632940277 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 88632940277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.adc_ctrl_clock_gating.6266845120574824008528389753549880015128552403368562825517219275873177869447
Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 528302015681 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 528302015681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_interrupt has 1 failures.

7.adc_ctrl_filters_interrupt.10862154027411010254259491369535880814297928731184616769324230634746573778010
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 82058758356 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 82058758356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 1 failures.

18.adc_ctrl_stress_all.34853734905392571186854476898768882740041507055496936800825370218007059540164
Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 82082556708 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 82082556708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---