AES/MASKED Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: `54711bc`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	85.510us	1	1	100.00
V1	smoke	aes_smoke	10.000s	313.576us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	180.152us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	142.760us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	329.989us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	206.482us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	161.982us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	142.760us	20	20	100.00
		aes_csr_aliasing	6.000s	206.482us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	313.576us	50	50	100.00
		aes_config_error	13.000s	360.563us	50	50	100.00
		aes_stress	10.000s	327.869us	50	50	100.00
V2	key_length	aes_smoke	10.000s	313.576us	50	50	100.00
		aes_config_error	13.000s	360.563us	50	50	100.00
		aes_stress	10.000s	327.869us	50	50	100.00
V2	back2back	aes_stress	10.000s	327.869us	50	50	100.00
		aes_b2b	39.000s	782.682us	50	50	100.00
V2	backpressure	aes_stress	10.000s	327.869us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	313.576us	50	50	100.00
		aes_config_error	13.000s	360.563us	50	50	100.00
		aes_stress	10.000s	327.869us	50	50	100.00
		aes_alert_reset	25.000s	2.927ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	63.560us	50	50	100.00
		aes_config_error	13.000s	360.563us	50	50	100.00
		aes_alert_reset	25.000s	2.927ms	50	50	100.00
V2	trigger_clear_test	aes_clear	30.000s	1.372ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	23.000s	3.842ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	25.000s	2.927ms	50	50	100.00
V2	stress	aes_stress	10.000s	327.869us	50	50	100.00
V2	sideload	aes_stress	10.000s	327.869us	50	50	100.00
		aes_sideload	8.000s	102.949us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	1.039ms	50	50	100.00
V2	stress_all	aes_stress_all	1.883m	5.616ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	131.996us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	208.163us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	208.163us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	180.152us	5	5	100.00
		aes_csr_rw	6.000s	142.760us	20	20	100.00
		aes_csr_aliasing	6.000s	206.482us	5	5	100.00
		aes_same_csr_outstanding	6.000s	97.620us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	180.152us	5	5	100.00
		aes_csr_rw	6.000s	142.760us	20	20	100.00
		aes_csr_aliasing	6.000s	206.482us	5	5	100.00
		aes_same_csr_outstanding	6.000s	97.620us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	57.000s	2.765ms	50	50	100.00
V2S	fault_inject	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_cipher_fi	48.000s	10.015ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	113.529us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	113.529us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	113.529us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	113.529us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	11.000s	2.041ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	530.259us	5	5	100.00
		aes_tl_intg_err	7.000s	240.093us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	240.093us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	25.000s	2.927ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	113.529us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	313.576us	50	50	100.00
		aes_stress	10.000s	327.869us	50	50	100.00
		aes_alert_reset	25.000s	2.927ms	50	50	100.00
		aes_core_fi	25.000s	10.011ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	113.529us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	92.923us	50	50	100.00
		aes_stress	10.000s	327.869us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	327.869us	50	50	100.00
		aes_sideload	8.000s	102.949us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	92.923us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	92.923us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	92.923us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	92.923us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	92.923us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	327.869us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	327.869us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	24.000s	4.578ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_cipher_fi	48.000s	10.015ms	338	350	96.57
		aes_ctr_fi	10.000s	593.981us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	24.000s	4.578ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_cipher_fi	48.000s	10.015ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.015ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	24.000s	4.578ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_ctr_fi	10.000s	593.981us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_cipher_fi	48.000s	10.015ms	338	350	96.57
		aes_ctr_fi	10.000s	593.981us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	25.000s	2.927ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_cipher_fi	48.000s	10.015ms	338	350	96.57
		aes_ctr_fi	10.000s	593.981us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_cipher_fi	48.000s	10.015ms	338	350	96.57
		aes_ctr_fi	10.000s	593.981us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_ctr_fi	10.000s	593.981us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	24.000s	4.578ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	284	300	94.67
		aes_cipher_fi	48.000s	10.015ms	338	350	96.57
V2S		TOTAL			955	985	96.95
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	26.000s	24.771ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1562	1602	97.50

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.42	98.63	96.52	99.44	95.81	97.99	97.78	98.96	97.99

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 17.aes_cipher_fi.28887228074574218607066002298474720307057803417996419564913605888441626803983
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015409998 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015409998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_cipher_fi.9479188245415871367794876070012959231738850934131536749466417487556867175347
    Line 133, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017868061 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017868061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 39.aes_control_fi.99807814961981567248356117541251927651690554686853104441269505479545747204083
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020045874 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020045874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 68.aes_control_fi.64952680294774378388547359698289804235993242788230694319985267063415867020136
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/68.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007304234 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007304234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
Job timed out after * minutes has 8 failures:
- Test aes_control_fi has 8 failures.
  - 49.aes_control_fi.112402588739656614107391361744493732377320982454994412568336197449878499035284
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 123.aes_control_fi.17183897133613127890572579107029720972534490923150200438056131680516383089820
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/123.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.20269685013021238698497633216225946834114854042499655484109615994262872832790
Line 541, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 460525523 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 460525523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.100753842938085162504537413823972390123716365482543408796448078359212945078386
Line 802, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 24771027090 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 24771027090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.45521776369447973460167894873985309770948284486784868971476462493222694218884
    Line 130, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 472575510 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 472575510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.70449573244294993138013176547210070281601246197907917565979043693322385573360
    Line 336, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1121363717 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1121363717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.25604789365474193966742585313246709606383317167298080771309235527220028017225
    Line 155, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 140087835 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 140087835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.7472688127347067143009809277932239516876131731238428629456823079313917687713
    Line 566, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2881574830 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2881574830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.85027350582218083260205973357518168442325720001702624292118950476290226333346
    Line 210, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 543074306 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 543074306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 45.aes_fi.4293947849610359553557221628320960758080641608891563806243674583073515651220
    Line 8432, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/45.aes_fi/latest/run.log
```
  UVM_FATAL @ 270970395 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 270970395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 65.aes_core_fi.41456300399684467601989851359495317047022580632172193819785178172170822644579
    Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011067629 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011067629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```