AES/UNMASKED Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: `54711bc`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	42.000s	95.395us	1	1	100.00
V1	smoke	aes_smoke	7.000s	82.841us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	103.307us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	70.424us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	1.900ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	594.049us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	105.814us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	70.424us	20	20	100.00
		aes_csr_aliasing	8.000s	594.049us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	82.841us	50	50	100.00
		aes_config_error	7.000s	125.484us	50	50	100.00
		aes_stress	8.000s	1.364ms	50	50	100.00
V2	key_length	aes_smoke	7.000s	82.841us	50	50	100.00
		aes_config_error	7.000s	125.484us	50	50	100.00
		aes_stress	8.000s	1.364ms	50	50	100.00
V2	back2back	aes_stress	8.000s	1.364ms	50	50	100.00
		aes_b2b	10.000s	822.241us	50	50	100.00
V2	backpressure	aes_stress	8.000s	1.364ms	50	50	100.00
V2	multi_message	aes_smoke	7.000s	82.841us	50	50	100.00
		aes_config_error	7.000s	125.484us	50	50	100.00
		aes_stress	8.000s	1.364ms	50	50	100.00
		aes_alert_reset	7.000s	381.996us	50	50	100.00
V2	failure_test	aes_man_cfg_err	27.000s	61.870us	50	50	100.00
		aes_config_error	7.000s	125.484us	50	50	100.00
		aes_alert_reset	7.000s	381.996us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	275.142us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	44.000s	315.176us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	381.996us	50	50	100.00
V2	stress	aes_stress	8.000s	1.364ms	50	50	100.00
V2	sideload	aes_stress	8.000s	1.364ms	50	50	100.00
		aes_sideload	7.000s	161.033us	50	50	100.00
V2	deinitialization	aes_deinit	32.000s	125.831us	50	50	100.00
V2	stress_all	aes_stress_all	37.000s	2.523ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	55.515us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	566.476us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	566.476us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	103.307us	5	5	100.00
		aes_csr_rw	5.000s	70.424us	20	20	100.00
		aes_csr_aliasing	8.000s	594.049us	5	5	100.00
		aes_same_csr_outstanding	6.000s	57.043us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	103.307us	5	5	100.00
		aes_csr_rw	5.000s	70.424us	20	20	100.00
		aes_csr_aliasing	8.000s	594.049us	5	5	100.00
		aes_same_csr_outstanding	6.000s	57.043us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	463.377us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_cipher_fi	34.000s	10.003ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	851.755us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	851.755us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	851.755us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	851.755us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	155.807us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	862.278us	5	5	100.00
		aes_tl_intg_err	7.000s	198.937us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	198.937us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	381.996us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	851.755us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	82.841us	50	50	100.00
		aes_stress	8.000s	1.364ms	50	50	100.00
		aes_alert_reset	7.000s	381.996us	50	50	100.00
		aes_core_fi	4.533m	10.015ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	851.755us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	53.022us	50	50	100.00
		aes_stress	8.000s	1.364ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	1.364ms	50	50	100.00
		aes_sideload	7.000s	161.033us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	53.022us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	53.022us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	53.022us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	53.022us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	53.022us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	1.364ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	1.364ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	232.803us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_cipher_fi	34.000s	10.003ms	328	350	93.71
		aes_ctr_fi	6.000s	134.353us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	232.803us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_cipher_fi	34.000s	10.003ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	34.000s	10.003ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	232.803us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_ctr_fi	6.000s	134.353us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_cipher_fi	34.000s	10.003ms	328	350	93.71
		aes_ctr_fi	6.000s	134.353us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	381.996us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_cipher_fi	34.000s	10.003ms	328	350	93.71
		aes_ctr_fi	6.000s	134.353us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_cipher_fi	34.000s	10.003ms	328	350	93.71
		aes_ctr_fi	6.000s	134.353us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_ctr_fi	6.000s	134.353us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	232.803us	49	50	98.00
		aes_control_fi	30.000s	10.003ms	278	300	92.67
		aes_cipher_fi	34.000s	10.003ms	328	350	93.71
V2S		TOTAL			937	985	95.13
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	32.000s	13.154ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1544	1602	96.38

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.32	97.67	94.75	98.84	93.51	98.07	93.33	98.65	97.59

Failure Buckets

Job timed out after * minutes has 22 failures:
- Test aes_control_fi has 11 failures.
  - 4.aes_control_fi.18857406031464393041674036624886041225885702571721548004984917658323319337448
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 29.aes_control_fi.70384015867402625173464343547866247890601913806105934406235778671925017263724
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 11 failures.
  - 59.aes_cipher_fi.23785885624737299982458280469676085608040218657306771220106255053016257678618
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 65.aes_cipher_fi.53654193853962570569964556739805903420447867983699299072711973057281634372805
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 53.aes_cipher_fi.63081149975521953888985053707891081849028242770240616097548449787911999869484
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/53.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020778458 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020778458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 67.aes_cipher_fi.6470214725280267862447655944684890724670729795372649877308615921641009147725
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/67.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006829740 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006829740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 55.aes_control_fi.54959801487406070040903491659722495987518480208490550188980399109149363781844
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012571193 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012571193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 61.aes_control_fi.81176451618594853977871382774029891053541363630404430127866143439884085111333
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10040405970 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10040405970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.9922083125079726579608883189660984961300766212056047278848653867785355735430
Line 515, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 240278529 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 240278529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.9641854801144653167920535996781507137351903662219470776889512499636078855638
Line 577, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13153938573 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 13153938573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 8.aes_stress_all_with_rand_reset.106303854795070051109217374728014817360393881580154227726653867676840612403394
    Line 787, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10377548046 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 10377548046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.40311798560983113806409703992286328614870256524116763151917370591740225227021
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  50747373 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  50747373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

0.aes_fi.20585825752091361488387604244729160467013194774042411557667044893630065387400
Line 933, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 13747519 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 13705852 PS)
  UVM_ERROR @  13747519 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  13747519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 6.aes_core_fi.100339131843461811530931352508408862530538732862938986530630198047569015967258
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015622621 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015622621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 13.aes_core_fi.18713091987669407548040569181650510801468407834322433313558029961328122873520
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015188642 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x1b39b984, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10015188642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 40.aes_core_fi.70440827302625980420491747357287883731612414839505719980756121443996877777056
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003249309 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003249309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```