| V1 |
smoke |
aon_timer_smoke |
2.510s |
600.919us |
5 |
5 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
3.660s |
693.472us |
5 |
5 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
2.950s |
420.626us |
20 |
20 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
19.310s |
14.199ms |
5 |
5 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
2.890s |
531.606us |
5 |
5 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
2.990s |
323.244us |
20 |
20 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
2.950s |
420.626us |
20 |
20 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.890s |
531.606us |
5 |
5 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
2.420s |
423.514us |
5 |
5 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
2.410s |
428.581us |
5 |
5 |
100.00 |
| V1 |
|
TOTAL |
|
|
70 |
70 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
1.441m |
61.973ms |
15 |
15 |
100.00 |
| V2 |
jump |
aon_timer_jump |
2.660s |
761.529us |
5 |
5 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
2.853m |
106.068ms |
15 |
15 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
2.910s |
494.565us |
50 |
50 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
2.990s |
436.474us |
50 |
50 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
4.340s |
899.736us |
20 |
20 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
4.340s |
899.736us |
20 |
20 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
3.660s |
693.472us |
5 |
5 |
100.00 |
|
|
aon_timer_csr_rw |
2.950s |
420.626us |
20 |
20 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.890s |
531.606us |
5 |
5 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
9.240s |
2.350ms |
20 |
20 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
3.660s |
693.472us |
5 |
5 |
100.00 |
|
|
aon_timer_csr_rw |
2.950s |
420.626us |
20 |
20 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.890s |
531.606us |
5 |
5 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
9.240s |
2.350ms |
20 |
20 |
100.00 |
| V2 |
|
TOTAL |
|
|
175 |
175 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
8.880s |
4.531ms |
5 |
5 |
100.00 |
|
|
aon_timer_tl_intg_err |
17.440s |
8.779ms |
20 |
20 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
17.440s |
8.779ms |
20 |
20 |
100.00 |
| V2S |
|
TOTAL |
|
|
25 |
25 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
2.290s |
583.207us |
5 |
5 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
3.100s |
588.156us |
5 |
5 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
9.900s |
3.170ms |
5 |
5 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
2.840s |
620.939us |
10 |
10 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
14.980s |
3.891ms |
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
43.490s |
12.700ms |
15 |
15 |
100.00 |
| V3 |
|
TOTAL |
|
|
45 |
45 |
100.00 |
|
|
TOTAL |
|
|
315 |
315 |
100.00 |