CSRNG Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	156.160us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	25.144us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	37.552us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	370.206us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	13.000s	635.286us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	97.268us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	37.552us	20	20	100.00
		csrng_csr_aliasing	13.000s	635.286us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	32.000s	1.841ms	200	200	100.00
V2	alerts	csrng_alert	55.000s	4.471ms	500	500	100.00
V2	err	csrng_err	8.000s	23.049us	500	500	100.00
V2	cmds	csrng_cmds	12.950m	70.255ms	50	50	100.00
V2	life cycle	csrng_cmds	12.950m	70.255ms	50	50	100.00
V2	stress_all	csrng_stress_all	21.767m	67.050ms	50	50	100.00
V2	intr_test	csrng_intr_test	6.000s	10.881us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	105.808us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	466.569us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	466.569us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	25.144us	5	5	100.00
		csrng_csr_rw	6.000s	37.552us	20	20	100.00
		csrng_csr_aliasing	13.000s	635.286us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	492.755us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	25.144us	5	5	100.00
		csrng_csr_rw	6.000s	37.552us	20	20	100.00
		csrng_csr_aliasing	13.000s	635.286us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	492.755us	20	20	100.00
V2		TOTAL			1440	1440	100.00
V2S	tl_intg_err	csrng_sec_cm	8.000s	117.369us	5	5	100.00
		csrng_tl_intg_err	17.000s	910.422us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	191.437us	50	50	100.00
		csrng_csr_rw	6.000s	37.552us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	55.000s	4.471ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.767m	67.050ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	55.000s	4.471ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.767m	67.050ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	55.000s	4.471ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	910.422us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
		csrng_sec_cm	8.000s	117.369us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	32.000s	1.841ms	200	200	100.00
		csrng_err	8.000s	23.049us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.117m	2.306ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1620	1630	99.39

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.73	98.61	96.62	99.94	97.48	92.02	100.00	97.19	90.46

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
  • Test csrng_stress_all_with_rand_reset has 9 failures.

    • 0.csrng_stress_all_with_rand_reset.37536813896691646881043488190902395167763720741073534558138351268900712452547
      Line 102, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 561887441 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 561887441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.csrng_stress_all_with_rand_reset.31511514464263693354632028963807153404252760955551185824391876794749799365129
      Line 105, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1071828346 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1071828346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 1.csrng_stress_all_with_rand_reset.10391035127208511560345030276384085373121258241663905699280911772406928463603
      Line 113, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   4801596 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
        UVM_INFO @   4801596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---