EDN Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.650s	18.554us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	2.460s	77.631us	5	5	100.00
V1	csr_rw	edn_csr_rw	2.450s	33.176us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.480s	700.786us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.760s	212.848us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.940s	190.008us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	2.450s	33.176us	20	20	100.00
		edn_csr_aliasing	2.760s	212.848us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	49.780s	2.257ms	300	300	100.00
V2	csrng_commands	edn_genbits	49.780s	2.257ms	300	300	100.00
V2	genbits	edn_genbits	49.780s	2.257ms	300	300	100.00
V2	interrupts	edn_intr	2.760s	21.729us	50	50	100.00
V2	alerts	edn_alert	3.020s	33.457us	200	200	100.00
V2	errs	edn_err	3.050s	35.133us	99	100	99.00
V2	disable	edn_disable	2.610s	34.375us	50	50	100.00
		edn_disable_auto_req_mode	2.880s	40.835us	49	50	98.00
V2	stress_all	edn_stress_all	9.590s	370.104us	50	50	100.00
V2	intr_test	edn_intr_test	2.510s	27.806us	50	50	100.00
V2	alert_test	edn_alert_test	3.650s	141.619us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.850s	283.369us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.850s	283.369us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	2.460s	77.631us	5	5	100.00
		edn_csr_rw	2.450s	33.176us	20	20	100.00
		edn_csr_aliasing	2.760s	212.848us	5	5	100.00
		edn_same_csr_outstanding	2.760s	39.073us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	2.460s	77.631us	5	5	100.00
		edn_csr_rw	2.450s	33.176us	20	20	100.00
		edn_csr_aliasing	2.760s	212.848us	5	5	100.00
		edn_same_csr_outstanding	2.760s	39.073us	20	20	100.00
V2		TOTAL			938	940	99.79
V2S	tl_intg_err	edn_sec_cm	9.540s	871.203us	5	5	100.00
		edn_tl_intg_err	4.350s	312.392us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.430s	38.030us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	3.020s	33.457us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.540s	871.203us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.540s	871.203us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.540s	871.203us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.540s	871.203us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	3.020s	33.457us	200	200	100.00
		edn_sec_cm	9.540s	871.203us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	3.020s	33.457us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.350s	312.392us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.037h	10.000s	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1106	1130	97.88

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.90	98.32	94.29	97.02	92.44	96.33	99.78	93.13

Failure Buckets

• Job timed out after * minutes has 20 failures:

  • Test edn_stress_all_with_rand_reset has 20 failures.

    • 2.edn_stress_all_with_rand_reset.111614299155600375795695709319683310178729072213928763944713564274590134150890
      Log /nightly/runs/scratch/master/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 4.edn_stress_all_with_rand_reset.96312466007125223919810398390285022809986320479152947734972016030921629570392
      Log /nightly/runs/scratch/master/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 18 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test edn_stress_all_with_rand_reset has 2 failures.

    • 3.edn_stress_all_with_rand_reset.78952900646661938802769123300217142462660795128172876417134531838325681831657
      Line 389, in log /nightly/runs/scratch/master/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 49.edn_stress_all_with_rand_reset.11065769460940240921425369486029322069824825822337575916669405663224493641399
      Line 350, in log /nightly/runs/scratch/master/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test edn_disable_auto_req_mode has 1 failures.

    • 9.edn_disable_auto_req_mode.55198523677090538987768962064141490157323015062226529588646864781932656872538
      Line 85, in log /nightly/runs/scratch/master/edn-sim-vcs/9.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'alert_tx_o[*].alert_p' has 1 failures:

  • Test edn_err has 1 failures.

    • 56.edn_err.9205422899240717614259843475080285384759486455357310724641903541836410924129
      Line 128, in log /nightly/runs/scratch/master/edn-sim-vcs/56.edn_err/latest/run.log

            Offending 'alert_tx_o[1].alert_p'
        UVM_ERROR @   4956874 ps: (edn.sv:143) [ASSERT FAILED] FpvSecCmCntAlertCheck_A
        UVM_INFO @   4956874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---