ENTROPY_SRC Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 41.437us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 40.000s 29.168us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 40.000s 26.730us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 44.000s 158.229us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 40.000s 166.236us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 40.000s 45.210us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 40.000s 26.730us 20 20 100.00
entropy_src_csr_aliasing 40.000s 166.236us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 41.437us 50 50 100.00
entropy_src_rng 7.100m 17.036ms 21 300 7.00
entropy_src_fw_ov 9.283m 20.094ms 180 300 60.00
V2 firmware_mode entropy_src_fw_ov 9.283m 20.094ms 180 300 60.00
V2 rng_mode entropy_src_rng 7.100m 17.036ms 21 300 7.00
V2 rng_max_rate entropy_src_rng_max_rate 4.417m 6.426ms 4 400 1.00
V2 health_checks entropy_src_rng 7.100m 17.036ms 21 300 7.00
V2 conditioning entropy_src_rng 7.100m 17.036ms 21 300 7.00
V2 interrupts entropy_src_rng 7.100m 17.036ms 21 300 7.00
entropy_src_intr 29.000s 1.599ms 50 50 100.00
V2 alerts entropy_src_rng 7.100m 17.036ms 21 300 7.00
entropy_src_functional_alerts 7.000s 249.243us 50 50 100.00
V2 stress_all entropy_src_stress_all 7.750m 19.322ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 8.417m 10.012ms 963 1000 96.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 30.000s 350.893us 50 50 100.00
V2 intr_test entropy_src_intr_test 40.000s 17.166us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 32.514us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 42.000s 122.563us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 42.000s 122.563us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 40.000s 29.168us 5 5 100.00
entropy_src_csr_rw 40.000s 26.730us 20 20 100.00
entropy_src_csr_aliasing 40.000s 166.236us 5 5 100.00
entropy_src_same_csr_outstanding 40.000s 116.776us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 40.000s 29.168us 5 5 100.00
entropy_src_csr_rw 40.000s 26.730us 20 20 100.00
entropy_src_csr_aliasing 40.000s 166.236us 5 5 100.00
entropy_src_same_csr_outstanding 40.000s 116.776us 20 20 100.00
V2 TOTAL 1508 2340 64.44
V2S tl_intg_err entropy_src_sec_cm 6.000s 161.047us 5 5 100.00
entropy_src_tl_intg_err 41.000s 175.943us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 7.100m 17.036ms 21 300 7.00
entropy_src_cfg_regwen 6.000s 15.623us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 7.100m 17.036ms 21 300 7.00
V2S sec_cm_config_redun entropy_src_rng 7.100m 17.036ms 21 300 7.00
V2S sec_cm_intersig_mubi entropy_src_rng 7.100m 17.036ms 21 300 7.00
entropy_src_fw_ov 9.283m 20.094ms 180 300 60.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 8.417m 10.012ms 963 1000 96.30
entropy_src_sec_cm 6.000s 161.047us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 8.417m 10.012ms 963 1000 96.30
entropy_src_sec_cm 6.000s 161.047us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 7.100m 17.036ms 21 300 7.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 8.417m 10.012ms 963 1000 96.30
entropy_src_sec_cm 6.000s 161.047us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 8.417m 10.012ms 963 1000 96.30
entropy_src_sec_cm 6.000s 161.047us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 8.417m 10.012ms 963 1000 96.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 249.243us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 41.000s 175.943us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 2.667m 7.914ms 3 50 6.00
V3 TOTAL 3 50 6.00
TOTAL 1691 2570 65.80

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
95.95 98.15 95.32 98.32 95.50 96.56 96.88 91.01 85.33

Failure Buckets