HMAC Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.620s	347.163us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.520s	39.276us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.430s	170.866us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.360s	3.064ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.770s	607.398us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	6.741m	72.637ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.430s	170.866us	20	20	100.00
		hmac_csr_aliasing	8.770s	607.398us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.558m	8.693ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.628m	1.844ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.499m	25.528ms	30	30	100.00
		hmac_test_sha384_vectors	8.902m	24.178ms	75	75	100.00
		hmac_test_sha512_vectors	8.761m	28.825ms	75	75	100.00
		hmac_test_hmac256_vectors	16.330s	364.261us	50	50	100.00
		hmac_test_hmac384_vectors	18.460s	4.292ms	60	60	100.00
		hmac_test_hmac512_vectors	19.510s	705.157us	75	75	100.00
V2	burst_wr	hmac_burst_wr	33.820s	644.580us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	20.358m	25.727ms	10	10	100.00
V2	error	hmac_error	1.309m	44.491ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.099m	85.485ms	10	10	100.00
V2	save_and_restore	hmac_smoke	13.620s	347.163us	10	10	100.00
		hmac_long_msg	1.558m	8.693ms	10	10	100.00
		hmac_back_pressure	1.628m	1.844ms	25	25	100.00
		hmac_datapath_stress	20.358m	25.727ms	10	10	100.00
		hmac_burst_wr	33.820s	644.580us	50	50	100.00
		hmac_stress_all	39.944m	99.865ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.620s	347.163us	10	10	100.00
		hmac_long_msg	1.558m	8.693ms	10	10	100.00
		hmac_back_pressure	1.628m	1.844ms	25	25	100.00
		hmac_datapath_stress	20.358m	25.727ms	10	10	100.00
		hmac_wipe_secret	1.099m	85.485ms	10	10	100.00
		hmac_test_sha256_vectors	4.499m	25.528ms	30	30	100.00
		hmac_test_sha384_vectors	8.902m	24.178ms	75	75	100.00
		hmac_test_sha512_vectors	8.761m	28.825ms	75	75	100.00
		hmac_test_hmac256_vectors	16.330s	364.261us	50	50	100.00
		hmac_test_hmac384_vectors	18.460s	4.292ms	60	60	100.00
		hmac_test_hmac512_vectors	19.510s	705.157us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.620s	347.163us	10	10	100.00
		hmac_long_msg	1.558m	8.693ms	10	10	100.00
		hmac_back_pressure	1.628m	1.844ms	25	25	100.00
		hmac_datapath_stress	20.358m	25.727ms	10	10	100.00
		hmac_burst_wr	33.820s	644.580us	50	50	100.00
		hmac_error	1.309m	44.491ms	10	10	100.00
		hmac_wipe_secret	1.099m	85.485ms	10	10	100.00
		hmac_test_sha256_vectors	4.499m	25.528ms	30	30	100.00
		hmac_test_sha384_vectors	8.902m	24.178ms	75	75	100.00
		hmac_test_sha512_vectors	8.761m	28.825ms	75	75	100.00
		hmac_test_hmac256_vectors	16.330s	364.261us	50	50	100.00
		hmac_test_hmac384_vectors	18.460s	4.292ms	60	60	100.00
		hmac_test_hmac512_vectors	19.510s	705.157us	75	75	100.00
		hmac_stress_all	39.944m	99.865ms	50	50	100.00
V2	stress_all	hmac_stress_all	39.944m	99.865ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.120s	48.020us	50	50	100.00
V2	intr_test	hmac_intr_test	2.120s	78.099us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.420s	2.453ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.420s	2.453ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.520s	39.276us	5	5	100.00
		hmac_csr_rw	2.430s	170.866us	20	20	100.00
		hmac_csr_aliasing	8.770s	607.398us	5	5	100.00
		hmac_same_csr_outstanding	3.930s	156.655us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.520s	39.276us	5	5	100.00
		hmac_csr_rw	2.430s	170.866us	20	20	100.00
		hmac_csr_aliasing	8.770s	607.398us	5	5	100.00
		hmac_same_csr_outstanding	3.930s	156.655us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.240s	54.861us	5	5	100.00
		hmac_tl_intg_err	6.220s	271.931us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.220s	271.931us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.620s	347.163us	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.230s	243.061us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	10.938m	350.156ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.970s	458.475us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.96	99.84	97.20	100.00	100.00	99.83	99.52	47.30