54711bc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.578m | 4.375ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 38.910s | 1.649ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 2.320s | 202.776us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.340s | 17.310us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.360s | 1.802ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 3.140s | 39.985us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.720s | 101.308us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.340s | 17.310us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 3.140s | 39.985us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 14.520s | 337.520us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 40.850m | 92.222ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 21.937m | 48.950ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 2.300s | 269.856us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.172m | 5.106ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.519m | 2.622ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.780s | 161.060us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 27.780s | 565.088us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.980s | 456.880us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 2.927m | 3.778ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 41.330s | 1.008ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.680s | 357.352us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 15.560s | 4.335ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 19.303m | 72.355ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 8.640s | 726.416us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.091m | 7.480ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 11.250s | 2.813ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.490s | 777.424us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.370s | 2.344ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 22.892m | 67.441ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.091m | 7.480ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.662m | 27.097ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 11.330s | 1.621ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.096m | 3.011ms | 42 | 50 | 84.00 |
| V2 | bad_address | i2c_target_bad_addr | 10.190s | 1.517ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 47.580s | 10.227ms | 21 | 50 | 42.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.660s | 2.833ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 3.240s | 143.421us | 47 | 50 | 94.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 21.937m | 48.950ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 11.389m | 24.321ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 41.330s | 1.008ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 32.340s | 2.564ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.560s | 1.211ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.170s | 2.242ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.460s | 385.405us | 32 | 50 | 64.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 22.200s | 2.611ms | 50 | 50 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.580s | 2.378ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 2.160s | 16.419us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 2.160s | 19.983us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.760s | 538.774us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.760s | 538.774us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 2.320s | 202.776us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.340s | 17.310us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.140s | 39.985us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.500s | 74.591us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 2.320s | 202.776us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.340s | 17.310us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.140s | 39.985us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.500s | 74.591us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1662 | 1792 | 92.75 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.940s | 572.789us | 20 | 20 | 100.00 |
| i2c_sec_cm | 2.850s | 186.448us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.940s | 572.789us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 48.620s | 4.705ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.820s | 451.140us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 18.190s | 1.336ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1842 | 2042 | 90.21 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.85 | 97.19 | 89.55 | 74.17 | 71.43 | 94.04 | 98.52 | 90.06 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 45 failures:
0.i2c_host_stress_all.9488878565174078405931402932017885364779428790150436146108073474018282068181
Line 165, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 58256536555 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4085498
1.i2c_host_stress_all.13346614160062285479428174015595674901999698972741372213739781466284583238198
Line 263, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 62174052109 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @15098416
... and 26 more failures.
2.i2c_host_mode_toggle.19534122531405296283204919559196755601664819283075619326689867546311522551635
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 102121869 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13217
4.i2c_host_mode_toggle.27105117855576506770528640725027931650179885932552749753140143915728294401304
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 102086532 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18647
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 37 failures:
0.i2c_target_unexp_stop.47630519703720935406014539801913500055153364712571712169857946211269690887101
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1195660523 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 88 [0x58])
UVM_INFO @ 1195660523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.50579138408421259992364663395627221806620265256103297653864172270080020237944
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 674350772 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 124 [0x7c])
UVM_INFO @ 674350772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
9.i2c_target_stress_all_with_rand_reset.114373135571861699556390611926848693855197274370689619869571015256099345295924
Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 300367428 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 125 [0x7d])
UVM_INFO @ 300367428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 29 failures:
0.i2c_target_hrst.255144059838569245994527736463130863768700156305716703153257328652138101402
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10450614563 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10450614563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.60319690425860585518284433681454441353931613827343501837923938617193797527566
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10454959705 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10454959705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
0.i2c_target_nack_txstretch.98214117849461047331941663063067538967320398853705441525105327336108816787496
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 151735293 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 151735293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.11264477112290360627827985594438657625663315846692393202903781913685735468804
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 152759623 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 152759623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.95325257706558551783145530718753789722481627353284233326480651887752624002060
Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 975862012 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 975862012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.106888877775800367208359339311870434161063095151929897056340929432376084159440
Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 849398716 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 849398716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.33095203679605451599256155212616886165556228813188615953634231382864367772668
Line 94, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 708605362 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 708605362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.96987328335267202506009686788652366960548369827716549894846981773849891205182
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1519268349 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1519268349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:
5.i2c_host_mode_toggle.98321747965322193691042585264821610233207472851905924016870352298799231424848
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 79041856 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
17.i2c_host_mode_toggle.39484943744850345585769578987176418789558521947583676969830148162920906798575
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 28216240 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 11 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 10 failures:
11.i2c_target_unexp_stop.43319103758223978233766406627114594117833744932529211221707043170901007586906
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2668207856 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2668207856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_unexp_stop.552553192667103237368864587955304052019840786845442911779120559526248853713
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 529987829 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 529987829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 8 failures:
6.i2c_target_stretch.62710230718134836373104773544627958430007774310225914927961896856479960327126
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002810339 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002810339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stretch.95538946507907643995981501703414811621661778893937398418737021715996443061596
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10051632408 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10051632408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
Test i2c_target_tx_stretch_ctrl has 2 failures.
19.i2c_target_tx_stretch_ctrl.71149382548467578652601100711867048774881730031608685282106165090731111639925
Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
26.i2c_target_tx_stretch_ctrl.51566643746204131517371300721024226253237492109186735196365128509666729998085
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 3 failures.
22.i2c_target_fifo_watermarks_tx.12160976134092578631362527084501556065913959273124877884128781865803991051860
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
30.i2c_target_fifo_watermarks_tx.93985189342845926594670566317166455378639617405800050817294347947014807326035
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:
2.i2c_target_unexp_stop.1057980374752336646479616944373134359096079457063280362159173734595100597057
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 922821432 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 922821432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_unexp_stop.89294669744942840544376132609763957798638310372216403098257303873559227393422
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 299382512 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 299382512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
7.i2c_host_stress_all.32822469873181584708064496936441898123199371500908119839868139596970616552680
Line 264, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 69430776491 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2906496
12.i2c_host_stress_all.26645993561620458461301570880286461291628831319360570113138270434813713703125
Line 218, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16050014108 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5210308
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
9.i2c_host_mode_toggle.35915903253344853589337331304198190549568135955429074909712261648525234761262
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 46124126 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x87ee3194, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 46124126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_host_mode_toggle.24049740936622547502666963758000522314247708426114922716074015649433425126815
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 31642367 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xd2804c94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 31642367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job timed out after * minutes has 3 failures:
22.i2c_host_stress_all.54156640176284150310257689599607931941762914700705444188012635690226594727157
Log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
26.i2c_host_stress_all.96342433172487040592038484379109588461364917996791226827712942132164847262526
Log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
0.i2c_same_csr_outstanding.111928868831430254023345617064179462779610311236973259522184494224506291019017
Line 72, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 386537297 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 386537297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
1.i2c_target_stress_all_with_rand_reset.47073828887250049919020055658905566629929653804665215998692770783437202222534
Line 137, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 941807178 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 941807178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
6.i2c_target_stress_all_with_rand_reset.54409619402494209860986742433446156724769956597954012684381876658684533016581
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 97147563 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 97147563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
21.i2c_target_intr_stress_wr.44629117045034874568928132376432512796024593239355171628659360542324105456338
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 51159243164 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 51159243164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
42.i2c_target_bad_addr.100959129873652146037912637660997488317840448431960417703402280149603383201490
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/42.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---