KEYMGR Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: `54711bc`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.060s	6.706ms	49	50	98.00
V1	random	keymgr_random	1.248m	25.057ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.820s	30.300us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.720s	35.587us	18	20	90.00
V1	csr_bit_bash	keymgr_csr_bit_bash	15.620s	14.303ms	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	9.780s	508.094us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.970s	54.891us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.720s	35.587us	18	20	90.00
		keymgr_csr_aliasing	9.780s	508.094us	4	5	80.00
V1		TOTAL			146	155	94.19
V2	cfgen_during_op	keymgr_cfg_regwen	55.260s	2.484ms	49	50	98.00
V2	sideload	keymgr_sideload	19.130s	755.872us	50	50	100.00
		keymgr_sideload_kmac	23.030s	995.103us	50	50	100.00
		keymgr_sideload_aes	44.960s	3.568ms	50	50	100.00
		keymgr_sideload_otbn	38.790s	23.407ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	25.480s	1.262ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	13.190s	601.378us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.020s	230.184us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	35.010s	32.201ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	32.260s	3.711ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	15.980s	854.386us	50	50	100.00
V2	stress_all	keymgr_stress_all	4.544m	17.397ms	45	50	90.00
V2	intr_test	keymgr_intr_test	2.300s	145.890us	50	50	100.00
V2	alert_test	keymgr_alert_test	3.060s	99.303us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.670s	1.576ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.670s	1.576ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.820s	30.300us	5	5	100.00
		keymgr_csr_rw	2.720s	35.587us	18	20	90.00
		keymgr_csr_aliasing	9.780s	508.094us	4	5	80.00
		keymgr_same_csr_outstanding	3.730s	110.353us	12	20	60.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.820s	30.300us	5	5	100.00
		keymgr_csr_rw	2.720s	35.587us	18	20	90.00
		keymgr_csr_aliasing	9.780s	508.094us	4	5	80.00
		keymgr_same_csr_outstanding	3.730s	110.353us	12	20	60.00
V2		TOTAL			724	740	97.84
V2S	sec_cm_additional_check	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
		keymgr_tl_intg_err	8.560s	747.021us	15	20	75.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.590s	257.984us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.590s	257.984us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.590s	257.984us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.590s	257.984us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.500s	405.362us	18	20	90.00
V2S	prim_count_check	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.560s	747.021us	15	20	75.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.590s	257.984us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	55.260s	2.484ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.248m	25.057ms	50	50	100.00
		keymgr_csr_rw	2.720s	35.587us	18	20	90.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.248m	25.057ms	50	50	100.00
		keymgr_csr_rw	2.720s	35.587us	18	20	90.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.248m	25.057ms	50	50	100.00
		keymgr_csr_rw	2.720s	35.587us	18	20	90.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	13.190s	601.378us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	32.260s	3.711ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	32.260s	3.711ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.248m	25.057ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	25.460s	3.455ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	30.270s	1.243ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	13.190s	601.378us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	30.270s	1.243ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	30.270s	1.243ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	30.270s	1.243ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.590s	2.551ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	30.270s	1.243ms	50	50	100.00
V2S		TOTAL			158	165	95.76
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.040s	3.265ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1056	1110	95.14

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.50	99.06	98.18	98.90	97.67	98.92	98.63	91.16

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 23 failures:

Test keymgr_csr_aliasing has 1 failures.

0.keymgr_csr_aliasing.60039508570750496277508270185371332233848707100208362600311509086396566957918
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @ 830085898 ps: (keymgr_csr_assert_fpv.sv:439) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @ 830085898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 8 failures.

0.keymgr_same_csr_outstanding.71206192074203291985760686590022916959926513102153669310339456299502843996846
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @  22412224 ps: (keymgr_csr_assert_fpv.sv:469) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @  22412224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_same_csr_outstanding.27576102286807301990075441421590264214006011036449005869598046497285035802209
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @  42883622 ps: (keymgr_csr_assert_fpv.sv:464) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @  42883622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_tl_intg_err has 5 failures.

2.keymgr_tl_intg_err.90374203620066705065471852650245710715195494626070753156925853611932020914896
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  14225141 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  14225141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_tl_intg_err.11525311870855910482490167512685586623777330726949786841852900505689672683719
Line 85, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @   5023552 ps: (keymgr_csr_assert_fpv.sv:444) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @   5023552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_bit_bash has 1 failures.

2.keymgr_csr_bit_bash.41316750726692301807283993274039414320274420728864152705690511432731084281843
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @ 697369068 ps: (keymgr_csr_assert_fpv.sv:414) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @ 697369068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_rw has 2 failures.

3.keymgr_csr_rw.48480601955781622541139793605706956392656320317099541886027211013409958963551
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @   6883074 ps: (keymgr_csr_assert_fpv.sv:459) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @   6883074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_csr_rw.75645958509843050993238572524138288765868401921381447156069739989866438695037
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @   4245306 ps: (keymgr_csr_assert_fpv.sv:459) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @   4245306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 1.keymgr_stress_all_with_rand_reset.94550729087281560883181065136220609791630067153288544477628006061563834516086
    Line 143, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 491991478 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 491991478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.62816715198699872656034557667221287270492662052702873555523863945881269558011
    Line 356, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 649186367 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 649186367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 6 failures:

Test keymgr_cfg_regwen has 1 failures.

38.keymgr_cfg_regwen.18152740524618314644646856594427710716837375947080818525905301024241005943321
Line 315, in log /nightly/runs/scratch/master/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  42763652 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  42763652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 3 failures.

40.keymgr_stress_all.28234136830652851203615595458153947996146656502829539752073992097173640477047
Line 317, in log /nightly/runs/scratch/master/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log

  UVM_ERROR @  89429448 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  89429448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.keymgr_stress_all.80779971375248063005890296902190940316351382371911153659535736778860389357747
Line 3095, in log /nightly/runs/scratch/master/keymgr-sim-vcs/43.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 722477494 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 722477494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_kmac_rsp_err has 1 failures.

41.keymgr_kmac_rsp_err.30115133407641677558430768463605459332262212110944289358326713654921777644873
Line 588, in log /nightly/runs/scratch/master/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 119809961 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 119809961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_smoke has 1 failures.

46.keymgr_smoke.87691486814527796387062105083530504188980207895010550006455849317566569625500
Line 94, in log /nightly/runs/scratch/master/keymgr-sim-vcs/46.keymgr_smoke/latest/run.log

  UVM_ERROR @   4950602 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   4950602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 11.keymgr_stress_all.25735798964567335134625820021437942625863662400472308126868697983442665962870
    Line 2124, in log /nightly/runs/scratch/master/keymgr-sim-vcs/11.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 6926799810 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_7
  UVM_INFO @ 6926799810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 17.keymgr_stress_all.30390673916551073038260580539480905917164976870017548299971011163837829579442
    Line 2526, in log /nightly/runs/scratch/master/keymgr-sim-vcs/17.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 5936118185 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @ 5936118185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 37.keymgr_hwsw_invalid_input.108162385166842798860548054721921175683238771957306097760632993840888383945040
    Line 546, in log /nightly/runs/scratch/master/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  54670001 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  54670001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```