KMAC/MASKED Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: `54711bc`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.520m	13.389ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.490s	31.927us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.620s	27.990us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.520s	5.205ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.740s	142.751us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.190s	972.234us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.620s	27.990us	20	20	100.00
		kmac_csr_aliasing	8.740s	142.751us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.150s	11.085us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.140s	40.627us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.826m	567.963ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.139m	59.649ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.881m	369.338ms	5	5	100.00
		kmac_test_vectors_sha3_256	24.104m	35.734ms	5	5	100.00
		kmac_test_vectors_sha3_384	25.693m	45.794ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.499m	227.772ms	5	5	100.00
		kmac_test_vectors_shake_128	40.389m	99.793ms	5	5	100.00
		kmac_test_vectors_shake_256	35.902m	375.569ms	5	5	100.00
		kmac_test_vectors_kmac	4.070s	126.307us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.590s	392.611us	5	5	100.00
V2	sideload	kmac_sideload	8.617m	78.246ms	50	50	100.00
V2	app	kmac_app	6.502m	28.614ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.816m	151.602ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.044m	65.289ms	50	50	100.00
V2	error	kmac_error	8.638m	41.061ms	50	50	100.00
V2	key_error	kmac_key_error	24.060s	13.171ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.420s	253.437us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.900s	6.412ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.560s	4.224ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.068m	13.667ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	32.610s	2.914ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.769m	128.438ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.350s	15.417us	50	50	100.00
V2	alert_test	kmac_alert_test	2.380s	21.436us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.970s	272.031us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.970s	272.031us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.490s	31.927us	5	5	100.00
		kmac_csr_rw	2.620s	27.990us	20	20	100.00
		kmac_csr_aliasing	8.740s	142.751us	5	5	100.00
		kmac_same_csr_outstanding	3.850s	218.428us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.490s	31.927us	5	5	100.00
		kmac_csr_rw	2.620s	27.990us	20	20	100.00
		kmac_csr_aliasing	8.740s	142.751us	5	5	100.00
		kmac_same_csr_outstanding	3.850s	218.428us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.200s	342.585us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.200s	342.585us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.200s	342.585us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.200s	342.585us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.990s	383.822us	14	20	70.00
V2S	tl_intg_err	kmac_sec_cm	1.512m	27.666ms	5	5	100.00
		kmac_tl_intg_err	5.850s	306.582us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.850s	306.582us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	32.610s	2.914ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.520m	13.389ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.617m	78.246ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.200s	342.585us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.512m	27.666ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.512m	27.666ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.512m	27.666ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.520m	13.389ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	32.610s	2.914ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.512m	27.666ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.265m	5.690ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.520m	13.389ms	50	50	100.00
V2S		TOTAL			65	75	86.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.904m	14.468ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			925	940	98.40

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.34	99.09	94.47	99.89	79.58	97.09	99.37	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 10 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

1.kmac_shadow_reg_errors_with_csr_rw.81112546907170917538306760066428336910845784035786335795845542642418845638235
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  57501774 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  57501774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.104890225549355946097320407660763546662923001027775101550899920037424166787138
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @ 126935364 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @ 126935364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_tl_intg_err has 4 failures.

3.kmac_tl_intg_err.96434585891121651087463852235093270879080589477729209243102965646862062885385
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  16951632 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  16951632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_tl_intg_err.105554811329999902889600729349215196199285565124101021545174789483347578974348
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  30522213 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  30522213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.79477521378321709446264459316411921591944851768444024149114140708796871487131
    Line 116, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 564599236 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 564599236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.71319260629947658627146683707135924103613620877614918094430719722201647773269
    Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  86036928 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @  86036928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.