KMAC/UNMASKED Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: `54711bc`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.116m	21.637ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.340s	22.238us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.710s	41.156us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.880s	1.308ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.290s	549.871us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.300s	489.262us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.710s	41.156us	20	20	100.00
		kmac_csr_aliasing	9.290s	549.871us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.270s	38.584us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.470s	43.403us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	46.728m	148.171ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.617m	234.252ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.002m	92.710ms	5	5	100.00
		kmac_test_vectors_sha3_256	22.848m	121.590ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.246m	57.259ms	5	5	100.00
		kmac_test_vectors_sha3_512	16.955m	527.403ms	5	5	100.00
		kmac_test_vectors_shake_128	30.111m	638.302ms	5	5	100.00
		kmac_test_vectors_shake_256	29.487m	72.810ms	5	5	100.00
		kmac_test_vectors_kmac	3.510s	203.175us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.530s	173.495us	5	5	100.00
V2	sideload	kmac_sideload	7.225m	40.145ms	50	50	100.00
V2	app	kmac_app	5.074m	34.553ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.491m	28.373ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.603m	58.883ms	50	50	100.00
V2	error	kmac_error	7.138m	78.843ms	50	50	100.00
V2	key_error	kmac_key_error	16.420s	6.492ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.334m	10.042ms	39	50	78.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.280s	7.928ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.630s	8.372ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.366m	77.013ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.810s	798.823us	50	50	100.00
V2	stress_all	kmac_stress_all	29.481m	209.576ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.580s	14.015us	50	50	100.00
V2	alert_test	kmac_alert_test	2.350s	23.096us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.500s	856.527us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.500s	856.527us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.340s	22.238us	5	5	100.00
		kmac_csr_rw	2.710s	41.156us	20	20	100.00
		kmac_csr_aliasing	9.290s	549.871us	5	5	100.00
		kmac_same_csr_outstanding	4.180s	137.333us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.340s	22.238us	5	5	100.00
		kmac_csr_rw	2.710s	41.156us	20	20	100.00
		kmac_csr_aliasing	9.290s	549.871us	5	5	100.00
		kmac_same_csr_outstanding	4.180s	137.333us	20	20	100.00
V2		TOTAL			729	740	98.51
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.930s	322.427us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.930s	322.427us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.930s	322.427us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.930s	322.427us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.040s	755.011us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	57.430s	16.072ms	5	5	100.00
		kmac_tl_intg_err	5.120s	257.911us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.120s	257.911us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.810s	798.823us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.116m	21.637ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.225m	40.145ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.930s	322.427us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	57.430s	16.072ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	57.430s	16.072ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	57.430s	16.072ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.116m	21.637ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.810s	798.823us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	57.430s	16.072ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.844m	132.255ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.116m	21.637ms	50	50	100.00
V2S		TOTAL			65	75	86.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.738m	37.073ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			912	940	97.02

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.07	97.17	94.38	100.00	75.21	95.98	99.35	96.41

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 10 failures:

Test kmac_tl_intg_err has 7 failures.

1.kmac_tl_intg_err.45767545765252576124435357871035861952925877570015398043185425628879314453460
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  10248693 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  10248693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_tl_intg_err.87424794739140149305082204838587930966582758138994576975265286237784807115892
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  12368373 ps: (kmac_csr_assert_fpv.sv:495) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  12368373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

3.kmac_shadow_reg_errors_with_csr_rw.5162366255732123355374077152722238508015352084538984385705524698170087143722
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
  UVM_ERROR @  17566059 ps: (kmac_csr_assert_fpv.sv:545) [ASSERT FAILED] prefix_10_rd_A
  UVM_INFO @  17566059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.kmac_shadow_reg_errors_with_csr_rw.59521148800657352976433125929308526423737646164282285694614256717151970680419
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  29900283 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  29900283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.60364462741019797526840865805997946380363590686969660043922440283417383013118
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  69838442 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @  69838442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.107974902214235460979098670708643457804237003885931750050868492978118191340939
    Line 282, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5433185275 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5433185275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 32.kmac_sideload_invalid.32858723612159912193380848700322669199351420588464905418688466708355225019538
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10046589991 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfe59f000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10046589991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 37.kmac_sideload_invalid.80939486928942538086716322617664290382424388128248971040651905010583127219958
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10046612004 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfba37000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10046612004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 1.kmac_sideload_invalid.33035593842277414361047220733476935766459459394943051904878479908866145875149
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10146532469 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa2a0f000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10146532469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 2.kmac_sideload_invalid.14084064709235664950394293272202870919329195710131512350461682022257723587882
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10406354071 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2d41e000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
  UVM_INFO @ 10406354071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 4.kmac_sideload_invalid.12276377358871569071524913943698995964239972331824399642189335737869963033259
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10042465468 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf06ed000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10042465468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 5.kmac_sideload_invalid.12751045040150840040874174644816158140483103875442780163244377014794836639131
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10231104683 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x399f9000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10231104683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 14.kmac_sideload_invalid.82398675830369776897932062969355146770960374558099255765527535285017803613548
    Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10269134036 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbd2e4000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
  UVM_INFO @ 10269134036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 18.kmac_sideload_invalid.90683881906071539063883324433311443199813314138553003063234750466086629096140
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10079753614 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7c7ec000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10079753614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 26.kmac_sideload_invalid.95691175320085691921920208886854930965733821553653269909017562631090186602255
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10126428172 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x37e3d000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10126428172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 28.kmac_sideload_invalid.83660336563602103039993173527095121938951232616202385246727635054163239410340
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10114477145 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb366d000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10114477145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```