OTBN Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	209.736us	1	1	100.00
V1	single_binary	otbn_single	1.483m	1.927ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	37.000s	25.580us	5	5	100.00
V1	csr_rw	otbn_csr_rw	35.000s	14.269us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	35.000s	130.613us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	36.000s	17.942us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	32.000s	189.542us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	35.000s	14.269us	20	20	100.00
		otbn_csr_aliasing	36.000s	17.942us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.150m	7.894ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	46.000s	124.459us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	41.000s	125.264us	10	10	100.00
V2	multi_error	otbn_multi_err	50.000s	820.206us	1	1	100.00
V2	back_to_back	otbn_multi	1.117m	408.579us	10	10	100.00
V2	stress_all	otbn_stress_all	3.067m	1.094ms	10	10	100.00
V2	lc_escalation	otbn_escalate	41.000s	490.931us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	30.979us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	160.607us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	21.848us	50	50	100.00
V2	intr_test	otbn_intr_test	42.000s	41.804us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	44.000s	176.551us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	44.000s	176.551us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	37.000s	25.580us	5	5	100.00
		otbn_csr_rw	35.000s	14.269us	20	20	100.00
		otbn_csr_aliasing	36.000s	17.942us	5	5	100.00
		otbn_same_csr_outstanding	31.000s	41.033us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	37.000s	25.580us	5	5	100.00
		otbn_csr_rw	35.000s	14.269us	20	20	100.00
		otbn_csr_aliasing	36.000s	17.942us	5	5	100.00
		otbn_same_csr_outstanding	31.000s	41.033us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	20.000s	71.296us	10	10	100.00
		otbn_dmem_err	15.000s	36.130us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	1.317m	334.233us	5	5	100.00
		otbn_controller_ispr_rdata_err	15.000s	64.034us	5	5	100.00
		otbn_mac_bignum_acc_err	30.000s	91.551us	4	5	80.00
		otbn_urnd_err	13.000s	36.198us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	17.814us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	41.998us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	32.218us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
		otbn_tl_intg_err	1.017m	519.595us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.217m	337.494us	16	20	80.00
V2S	prim_fsm_check	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	209.736us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	36.130us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	20.000s	71.296us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.017m	519.595us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	41.000s	490.931us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	20.000s	71.296us	10	10	100.00
		otbn_dmem_err	15.000s	36.130us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	30.979us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	17.814us	5	5	100.00
		otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.483m	1.927ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	20.000s	71.296us	10	10	100.00
		otbn_dmem_err	15.000s	36.130us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	30.979us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	17.814us	5	5	100.00
		otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	41.000s	490.931us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	20.000s	71.296us	10	10	100.00
		otbn_dmem_err	15.000s	36.130us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	30.979us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	17.814us	5	5	100.00
		otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.483m	1.927ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	17.000s	54.305us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	26.361us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	46.000s	239.891us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	46.000s	239.891us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	19.000s	78.469us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	240.872us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	27.803us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	27.803us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	52.428us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.483m	1.927ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.483m	1.927ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.483m	1.927ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.117m	408.579us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.483m	1.927ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.483m	1.927ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	75.858us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.483m	1.927ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.417m	2.150ms	3	5	60.00
V2S		TOTAL			152	163	93.25
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.217m	3.718ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			566	585	96.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.06	99.64	96.00	99.72	93.12	93.78	97.44	91.13	100.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:

  • Test otbn_stress_all_with_rand_reset has 5 failures.

    • 2.otbn_stress_all_with_rand_reset.78752413738426573510207006247377917454346207307749408792839898056944650322445
      Line 239, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1549761057 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1549761057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.otbn_stress_all_with_rand_reset.62161834209017082222492788207666726990615318440185651946970243263566246578590
      Line 169, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 153635524 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 153635524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

  • Test otbn_sec_wipe_err has 2 failures.

    • 0.otbn_sec_wipe_err.35376013910387175274151417957838046013570438275476888672269349750945973017611
      Line 117, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 45018289 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  45018289 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  45018289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.otbn_sec_wipe_err.30796653615551793476441793225656490575313883826160236186055669226322514155152
      Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 20828035 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  20828035 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  20828035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_ctrl_redun has 1 failures.

    • 6.otbn_ctrl_redun.81175109463180347428582664045458259090791006608549743789154514158899077209940
      Line 105, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_ctrl_redun/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 39207832 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  39207832 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  39207832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_escalate has 1 failures.

    • 44.otbn_escalate.69196480035217961649508866707682302978564685316455909757706047939157153067113
      Line 119, in log /nightly/runs/scratch/master/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10099371 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  10099371 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  10099371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 4 failures:

  • Test otbn_passthru_mem_tl_intg_err has 4 failures.

    • 1.otbn_passthru_mem_tl_intg_err.87872623767289528128066927920193134341318057155118579819439345780266145505017
      Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @   3330967 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
        UVM_INFO @   3330967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.otbn_passthru_mem_tl_intg_err.108904091556851399016635547736354022262484830701152231736114908938043472865160
      Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @   2258422 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
        UVM_INFO @   2258422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

  • Test otbn_sec_cm has 2 failures.

    • 0.otbn_sec_cm.83506293757529771040472044358045989931136805534867737938958794277276260423792
      Line 83, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 2933454 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 2933454 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @   2933454 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @   2933454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.otbn_sec_cm.54804807135403797671830757242273803825022011776117400931485986145189341576696
      Line 134, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 480578938 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 480578938 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @ 480578938 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @ 480578938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.15598340116199933749072062316890407741364834359801278903116990891942046076197
      Line 224, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 294520948 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 294520948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_mac_bignum_acc_err has 1 failures.

    • 2.otbn_mac_bignum_acc_err.56643855390958821953932183577868900677027112797056929656028267173617449354270
      Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_mac_bignum_acc_err/latest/run.log

        UVM_FATAL @  91551199 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  91551199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 6.otbn_stress_all_with_rand_reset.55421840446249590070985164233226152303946992330930523171754955384714970419743
      Line 159, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  36216225 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @  36216225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:

  • Test otbn_partial_wipe has 1 failures.

    • 8.otbn_partial_wipe.54279622741419858973584728699899440574789014677871864777211800030206496138099
      Line 104, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 49075103 PS) Assertion tb.MatchingStatus_A has failed
        UVM_ERROR @  49075103 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
        UVM_INFO @  49075103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---