54711bc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 9.000s | 118.791us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 17.395us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 7.000s | 26.463us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 10.000s | 128.158us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 93.346us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 19.180us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 7.000s | 26.463us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 93.346us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 54.533m | 600.000ms | 28 | 50 | 56.00 |
| V2 | cnt_rollover | cnt_rollover | 1.700m | 5.484ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 6.000s | 36.532us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.879h | 2.845s | 13 | 50 | 26.00 |
| V2 | alert_test | pattgen_alert_test | 5.000s | 12.502us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 16.729us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 7.000s | 1.164ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 7.000s | 1.164ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 17.395us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 7.000s | 26.463us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 93.346us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 42.299us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 17.395us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 7.000s | 26.463us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 93.346us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 42.299us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 281 | 340 | 82.65 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 6.000s | 195.463us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 5.000s | 584.266us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 6.000s | 195.463us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.600m | 25.659ms | 3 | 50 | 6.00 |
| V3 | TOTAL | 3 | 50 | 6.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.133m | 10.017ms | 31 | 50 | 62.00 | |
| TOTAL | 445 | 570 | 78.07 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.80 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:
0.pattgen_stress_all_with_rand_reset.109070769796936052254423903837940505651884667116074216369241115468858731106613
Line 348, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1032981012 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1032987134 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1032987134 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 8/10
UVM_INFO @ 1033037639 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.31549990356421204481268629910169530879784270387504975409459922931473392130632
Line 317, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17486077709 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 17486121189 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 17486121189 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 6/10
UVM_INFO @ 17486254523 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 44 more failures.
Job timed out after * minutes has 27 failures:
0.pattgen_perf.101079199441163741745048069126210017214763565935549473653594563658970673082569
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Job timed out after 60 minutes
6.pattgen_perf.6912913309318166099835605109215010427584449693418327553752388011012067841618
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 8 more failures.
0.pattgen_stress_all.90307334585029194242440833397335460583045031155886341434391476959281498054394
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
11.pattgen_stress_all.35279531150478233099535350824251579178644554279462520891266805695920684053235
Log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 15 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 19 failures:
2.pattgen_stress_all.92012366690563120041494353880757803671626805757008220101574453202855985674509
Line 146, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_ERROR @ 95829894985 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @13124
5.pattgen_stress_all.80894867065765029101509532036283613799302010913439464069409046127431080008348
Line 130, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
UVM_ERROR @ 1344835007287 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
-----------------------------------------
Name Type Size Value
-----------------------------------------
exp_item pattgen_item - @544302
... and 17 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:
1.pattgen_perf.72017099559457942087010270918980823985586315881807391072146929496920520135877
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pattgen_perf.92553875914380291261174647328581854302681558964429561724083061891716267545691
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
4.pattgen_stress_all.4540464927006924031555962566732572818692206307666550880966447984698797466806
Line 131, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 3 failures:
4.pattgen_inactive_level.52472047979712750871840359804891871949199961779885771315487873777205925114781
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10039963302 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x10b22190, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10039963302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.pattgen_inactive_level.101460386929136056327368218976436517127367206642803893912827163679773185344563
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10020945998 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x74760750, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10020945998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
6.pattgen_inactive_level.71309461290738774238922462655532681675938556891776101847559749568671879578183
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10028004059 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa8887ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10028004059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.pattgen_inactive_level.1258602866233356826140976586644993386736193700049067699532176077827117402650
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10008947033 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf2435c10, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10008947033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
10.pattgen_inactive_level.38769209155120406997077640115297597363691205046899481571998429619095384250882
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10005712084 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc994e550, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10005712084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.pattgen_inactive_level.46515657837591017404084376957095480304160299385909248194808822134666201758582
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004669559 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x11df6050, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004669559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
12.pattgen_inactive_level.108944128562655537075872678270802646881133830838228400635390034271174843863038
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002486694 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x26bd2450, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10002486694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.pattgen_inactive_level.37959352746083366593687424689637896129786413203449913049304723215655853463101
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10007046593 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xad0f890, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10007046593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
3.pattgen_inactive_level.96109101716412730862825357500477681887416477023414520456417854765449889380585
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10195778659 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa9390b90, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10195778659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
11.pattgen_inactive_level.27034608546499068232839283343537886769491606057930936615229311490355125122217
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10027571948 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xcc99d150, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10027571948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
14.pattgen_inactive_level.61732207059093945795461270728688167497408058062677622223816003030360133865284
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10016557108 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1b7c7110, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10016557108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
23.pattgen_inactive_level.72039893348422981929602982957943410197253977234434079406365938908524333960566
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10008277649 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x403c0fd0, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10008277649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
25.pattgen_inactive_level.42265288885170187663643519041864653698678129413806869500914109530491258912408
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10222292226 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5abaf0d0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10222292226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
34.pattgen_inactive_level.32338962492435564455964023864599100867955798501946999323757447384005069721314
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10020817537 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x8e9b9450, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10020817537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
37.pattgen_inactive_level.114683866446094762618439775194867422132468442381758561981083113507807711056688
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006906209 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x7569fe50, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
UVM_INFO @ 10006906209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
38.pattgen_inactive_level.36529953300326824234877510454581588828186515738390127369640818598162822916404
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10058365841 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x63d7ce90, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10058365841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
38.pattgen_stress_all_with_rand_reset.112005577558932867106327056463897498496432088143763589118542333101829546416819
Line 128, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 419988367 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
39.pattgen_inactive_level.14557110826597980222570726689502883145339536673499696894632196585804926175216
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006895213 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xff4ddc90, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10006895213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
41.pattgen_inactive_level.18131834815612804112153700561499938321461832135999086857663562707946269798174
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10028802910 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x746946d0, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10028802910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---