ROM_CTRL/32KB Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.300s	300.594us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.480s	399.808us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.720s	556.786us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.630s	210.298us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.030s	172.021us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.290s	1.633ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.720s	556.786us	20	20	100.00
		rom_ctrl_csr_aliasing	8.030s	172.021us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.260s	174.381us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.000s	302.653us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.740s	138.947us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	35.310s	4.177ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.470s	717.375us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	10.230s	551.548us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.990s	6.243ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.990s	6.243ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.480s	399.808us	5	5	100.00
		rom_ctrl_csr_rw	8.720s	556.786us	20	20	100.00
		rom_ctrl_csr_aliasing	8.030s	172.021us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.070s	178.589us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.480s	399.808us	5	5	100.00
		rom_ctrl_csr_rw	8.720s	556.786us	20	20	100.00
		rom_ctrl_csr_aliasing	8.030s	172.021us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.070s	178.589us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	28.690s	866.443us	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.891m	2.831ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.067m	540.230us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.891m	2.831ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.891m	2.831ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.891m	2.831ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.891m	2.831ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.300s	300.594us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.300s	300.594us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.300s	300.594us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.067m	540.230us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
		rom_ctrl_kmac_err_chk	9.470s	717.375us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.803m	8.926ms	16	20	80.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	28.690s	866.443us	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.891m	2.831ms	5	5	100.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.749m	16.169ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			262	266	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	100.00	99.41	100.00	100.00	100.00	98.97	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

    • 3.rom_ctrl_corrupt_sig_fatal_chk.4205624337730868710257292744637055289778699199133811348700323657968992515546
      Line 86, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 439415130 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 439415130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.rom_ctrl_corrupt_sig_fatal_chk.1699378636800990425636272623817962246859076547875886757602388271839012774331
      Line 93, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 3591729516 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 3591729516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.