ROM_CTRL/64KB Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.890s 722.967us 2 2 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 18.540s 2.862ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 11.000s 305.180us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 9.950s 3.120ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 10.580s 1.683ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 15.330s 4.162ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 11.000s 305.180us 20 20 100.00
rom_ctrl_csr_aliasing 10.580s 1.683ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 9.760s 545.846us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 10.610s 3.979ms 5 5 100.00
V1 TOTAL 67 67 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.050s 1.203ms 2 2 100.00
V2 stress_all rom_ctrl_stress_all 52.310s 1.092ms 20 20 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 19.170s 575.722us 2 2 100.00
V2 alert_test rom_ctrl_alert_test 12.190s 297.858us 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 14.920s 294.132us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 14.920s 294.132us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 18.540s 2.862ms 5 5 100.00
rom_ctrl_csr_rw 11.000s 305.180us 20 20 100.00
rom_ctrl_csr_aliasing 10.580s 1.683ms 5 5 100.00
rom_ctrl_same_csr_outstanding 19.980s 1.072ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 18.540s 2.862ms 5 5 100.00
rom_ctrl_csr_rw 11.000s 305.180us 20 20 100.00
rom_ctrl_csr_aliasing 10.580s 1.683ms 5 5 100.00
rom_ctrl_same_csr_outstanding 19.980s 1.072ms 20 20 100.00
V2 TOTAL 114 114 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 53.930s 6.948ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 7.345m 658.004us 5 5 100.00
rom_ctrl_tl_intg_err 2.062m 991.100us 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 7.345m 658.004us 5 5 100.00
V2S prim_count_check rom_ctrl_sec_cm 7.345m 658.004us 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 7.345m 658.004us 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 7.345m 658.004us 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.890s 722.967us 2 2 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.890s 722.967us 2 2 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.890s 722.967us 2 2 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 2.062m 991.100us 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
rom_ctrl_kmac_err_chk 19.170s 575.722us 2 2 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.417m 18.910ms 20 20 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 53.930s 6.948ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 7.345m 658.004us 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 7.951m 5.818ms 20 20 100.00
V3 TOTAL 20 20 100.00
TOTAL 266 266 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.67 100.00 99.41 100.00 100.00 100.00 98.97 99.28