RV_TIMER Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	3.570s	14.945us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.060s	49.905us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.220s	11.472us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.820s	1.495ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.220s	17.511us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.330s	350.564us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.220s	11.472us	20	20	100.00
		rv_timer_csr_aliasing	2.220s	17.511us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	13.700s	36.174ms	20	20	100.00
V2	disabled	rv_timer_disabled	5.250s	2.522ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.421m	183.189ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.421m	183.189ms	10	10	100.00
V2	stress	rv_timer_stress_all	13.430s	10.614ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	3.680s	125.034us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.070s	48.405us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.180s	62.899us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.180s	62.899us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.060s	49.905us	5	5	100.00
		rv_timer_csr_rw	2.220s	11.472us	20	20	100.00
		rv_timer_csr_aliasing	2.220s	17.511us	5	5	100.00
		rv_timer_same_csr_outstanding	2.450s	56.347us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.060s	49.905us	5	5	100.00
		rv_timer_csr_rw	2.220s	11.472us	20	20	100.00
		rv_timer_csr_aliasing	2.220s	17.511us	5	5	100.00
		rv_timer_same_csr_outstanding	2.450s	56.347us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	3.860s	668.526us	5	5	100.00
		rv_timer_tl_intg_err	2.620s	241.015us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.620s	241.015us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	56.350s	6.786ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	3.640s	19.100us	10	10	100.00
		rv_timer_max	3.610s	28.409us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00