SPI_DEVICE/1R1W Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: `54711bc`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.519m	544.278ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	3.020s	42.002us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.000s	147.977us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.770s	532.260us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.320s	1.849ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.600s	60.010us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.000s	147.977us	20	20	100.00
		spi_device_csr_aliasing	22.320s	1.849ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.250s	14.635us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.830s	61.809us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.630s	20.124us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.330s	3.434us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.720s	3.281us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.010s	412.600us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.010s	412.600us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.960s	10.154ms	50	50	100.00
		spi_device_tpm_sts_read	2.710s	90.009us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	38.100s	21.603ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.610s	16.006ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.920s	18.088ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.920s	18.088ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.970s	31.542ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.970s	31.542ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.970s	31.542ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.970s	31.542ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.970s	31.542ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	46.760s	20.967ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.249m	31.392ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.249m	31.392ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.249m	31.392ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	50.480s	8.101ms	50	50	100.00
		spi_device_read_buffer_direct	19.960s	1.976ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.249m	31.392ms	50	50	100.00
		spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.939m	329.903ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.180s	15.761ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.180s	15.761ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.519m	544.278ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.762m	78.882ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.789m	188.777ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.370s	23.753us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.410s	50.809us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.050s	543.704us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.050s	543.704us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	3.020s	42.002us	5	5	100.00
		spi_device_csr_rw	4.000s	147.977us	20	20	100.00
		spi_device_csr_aliasing	22.320s	1.849ms	5	5	100.00
		spi_device_same_csr_outstanding	6.290s	225.443us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	3.020s	42.002us	5	5	100.00
		spi_device_csr_rw	4.000s	147.977us	20	20	100.00
		spi_device_csr_aliasing	22.320s	1.849ms	5	5	100.00
		spi_device_same_csr_outstanding	6.290s	225.443us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.420s	165.611us	5	5	100.00
		spi_device_tl_intg_err	19.060s	1.156ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.060s	1.156ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	46.314m	1.500s	48	50	96.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	98.98	96.55	83.54	89.36	98.39	95.66	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.54007442021722825732761006445341667661253506113299508407881235219947655648344
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1158806 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[58])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1158806 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1158806 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[954])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.41335012840819054387899855099367231338623975857331690384841664889165485058791
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3811571 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[42])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3811571 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3811571 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[938])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.56293513227036163695396269217833548954551554377248430251074576793314070199485
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    786061 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb639b7 [101101100011100110110111] vs 0x0 [0])
  UVM_ERROR @    830061 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xabeade [101010111110101011011110] vs 0x0 [0])
  UVM_ERROR @    857061 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x82bdd0 [100000101011110111010000] vs 0x0 [0])
  UVM_ERROR @    928061 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5e4557 [10111100100010101010111] vs 0x0 [0])
  UVM_ERROR @   1022061 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd28992 [110100101000100110010010] vs 0x0 [0])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 23.spi_device_flash_mode_ignore_cmds.67589713109588149102147396019366104857510020197781449479512177557486149028216
    Log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 24.spi_device_flash_mode_ignore_cmds.99766517651177625252758590044759191961300886461248005334170399012264070943155
    Line 74, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```