SPI_DEVICE/2P Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.667m	62.188ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.970s	42.915us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.220s	101.454us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.950s	2.735ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.160s	4.799ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.480s	670.091us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.220s	101.454us	20	20	100.00
		spi_device_csr_aliasing	21.160s	4.799ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.400s	58.945us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.490s	59.448us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.470s	152.770us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.710s	334.354us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	2.000s	34.187us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.790s	252.216us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.790s	252.216us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	31.910s	21.683ms	50	50	100.00
		spi_device_tpm_sts_read	2.850s	172.355us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.220s	32.225ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.520s	33.100ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.140s	61.882ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.140s	61.882ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.060s	16.374ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.060s	16.374ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.060s	16.374ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.060s	16.374ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.060s	16.374ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.630s	36.381ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.378m	23.406ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.378m	23.406ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.378m	23.406ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.044m	4.882ms	50	50	100.00
		spi_device_read_buffer_direct	18.930s	1.786ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.378m	23.406ms	50	50	100.00
		spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	4.394m	214.992ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.030s	3.607ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.030s	3.607ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.667m	62.188ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.655m	405.086ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.371m	382.082ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.430s	25.090us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.470s	34.735us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.000s	220.086us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.000s	220.086us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.970s	42.915us	5	5	100.00
		spi_device_csr_rw	4.220s	101.454us	20	20	100.00
		spi_device_csr_aliasing	21.160s	4.799ms	5	5	100.00
		spi_device_same_csr_outstanding	6.150s	1.581ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.970s	42.915us	5	5	100.00
		spi_device_csr_rw	4.220s	101.454us	20	20	100.00
		spi_device_csr_aliasing	21.160s	4.799ms	5	5	100.00
		spi_device_same_csr_outstanding	6.150s	1.581ms	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	3.090s	809.609us	5	5	100.00
		spi_device_tl_intg_err	18.350s	2.075ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.350s	2.075ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.113m	164.402ms	50	50	100.00
		TOTAL			1151	1151	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.17	99.04	96.66	87.74	89.36	98.47	95.65	99.26