SPI_HOST Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.917m	36.046ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	20.020us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	26.543us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	198.147us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	31.429us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	32.509us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	26.543us	20	20	100.00
		spi_host_csr_aliasing	5.000s	31.429us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	48.980us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	29.213us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	37.000s	51.452us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	38.000s	174.128us	50	50	100.00
		spi_host_error_cmd	37.000s	21.231us	50	50	100.00
		spi_host_event	17.783m	71.521ms	50	50	100.00
V2	clock_rate	spi_host_speed	38.000s	62.351us	49	50	98.00
V2	speed	spi_host_speed	38.000s	62.351us	49	50	98.00
V2	chip_select_timing	spi_host_speed	38.000s	62.351us	49	50	98.00
V2	sw_reset	spi_host_sw_reset	3.033m	7.190ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	28.000s	67.405us	50	50	100.00
V2	cpol_cpha	spi_host_speed	38.000s	62.351us	49	50	98.00
V2	full_cycle	spi_host_speed	38.000s	62.351us	49	50	98.00
V2	duplex	spi_host_smoke	2.917m	36.046ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.917m	36.046ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.217m	5.598ms	50	50	100.00
V2	spien	spi_host_spien	3.917m	6.755ms	50	50	100.00
V2	stall	spi_host_status_stall	19.817m	77.582ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	39.000s	3.157ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	38.000s	174.128us	50	50	100.00
V2	alert_test	spi_host_alert_test	8.000s	20.736us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	17.304us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	122.359us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	122.359us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	20.020us	5	5	100.00
		spi_host_csr_rw	5.000s	26.543us	20	20	100.00
		spi_host_csr_aliasing	5.000s	31.429us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	16.575us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	20.020us	5	5	100.00
		spi_host_csr_rw	5.000s	26.543us	20	20	100.00
		spi_host_csr_aliasing	5.000s	31.429us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	16.575us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	97.681us	20	20	100.00
		spi_host_sec_cm	9.000s	231.225us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	97.681us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	12.917m	100.053ms	9	10	90.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.29	96.83	93.37	98.69	94.36	88.02	100.00	97.27	90.42

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:234) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 1.spi_host_upper_range_clkdiv.56575841520481181951333203311668243817545362492182454393397331961424996404950
      Line 150, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100052725872 ps: (spi_host_base_vseq.sv:234) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0x6968d494, Comparison=CompareOpEq, exp_data=0x0, call_count=14
        UVM_INFO @ 100052725872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:234) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 2.spi_host_speed.92164522327775391325289254149740741103340245244250109768350172010392296345215
      Line 195, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/2.spi_host_speed/latest/run.log

        UVM_FATAL @ 10033309639 ps: (spi_host_base_vseq.sv:234) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xec0be014, Comparison=CompareOpEq, exp_data=0x0, call_count=29
        UVM_INFO @ 10033309639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---