SRAM_CTRL/MAIN Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.281m	23.055ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.260s	54.117us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.240s	14.758us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.300s	157.118us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.200s	25.380us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.380s	1.496ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.240s	14.758us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	25.380us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.211m	28.755ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.039m	6.376ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	20.904m	24.844ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.707m	21.513ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	45.798m	1.643s	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.077m	28.895ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.819m	68.409ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.433m	11.713ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.605m	3.847ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.331m	62.240ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.701m	5.864ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.554m	3.243ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.757m	1.866ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.199m	17.339ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.430s	3.047ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.883h	942.803ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.170s	14.361us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.590s	579.996us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.590s	579.996us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.260s	54.117us	5	5	100.00
		sram_ctrl_csr_rw	2.240s	14.758us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	25.380us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.260s	16.425us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.260s	54.117us	5	5	100.00
		sram_ctrl_csr_rw	2.240s	14.758us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	25.380us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.260s	16.425us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	56.170s	7.135ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.970s	13.314us	0	5	0.00
		sram_ctrl_tl_intg_err	4.420s	1.514ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.970s	13.314us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.420s	1.514ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.199m	17.339ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.199m	17.339ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.240s	14.758us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.433m	11.713ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.433m	11.713ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.433m	11.713ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.819m	68.409ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	14.940s	13.303ms	40	50	80.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	56.170s	7.135ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.550s	4.705ms	37	50	74.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.281m	23.055ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.281m	23.055ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.433m	11.713ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.970s	13.314us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.819m	68.409ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.970s	13.314us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.970s	13.314us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.281m	23.055ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.970s	13.314us	0	5	0.00
V2S		TOTAL			117	145	80.69
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.048m	3.187ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1162	1190	97.65

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.29	93.01	85.18	100.00	98.03	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 13 failures:
  • Test sram_ctrl_readback_err has 13 failures.

    • 4.sram_ctrl_readback_err.27010008193717577436533528945586045792755524458098756458243589673851763308051
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 686023646 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x5c) != exp (0x6e)
        UVM_INFO @ 686023646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.sram_ctrl_readback_err.42311827285703137865679322409368880016050385731337420255932739011983798093637
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 677449337 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x59) != exp (0x23)
        UVM_INFO @ 677449337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 11 more failures.

• Offending 'reqfifo_rvalid' has 10 failures:
  • Test sram_ctrl_mubi_enc_err has 10 failures.

    • 0.sram_ctrl_mubi_enc_err.35753375787537973318737236277036773323144498074162656841178805297609996214251
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2738895177 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2738895177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_mubi_enc_err.80621410713649078944394038795786385500036494690925885953305943275292142894122
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 725898344 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 725898344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.105051964194364411053657287699618515263015294595193024997091406539404403376996
      Line 103, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  13313589 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  13313589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.98598486207476028902350932304049216000590812435021337109193767475576156099233
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3418292 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3418292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.85451964564774850628632976205507504366046471033937290842583435574915602059854
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   6483922 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   6483922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---