SRAM_CTRL/RET Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: `54711bc`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.806m	159.765us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.150s	67.799us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.330s	22.459us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.360s	444.823us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.070s	43.250us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.330s	140.342us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.330s	22.459us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	43.250us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	16.960s	5.699ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.980s	449.194us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	29.695m	75.834ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.832m	8.556ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.494m	9.555ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	26.671m	4.014ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.720s	4.049ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.349m	3.196ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.589m	408.635us	50	50	100.00
		sram_ctrl_partial_access_b2b	12.574m	31.577ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.782m	1.183ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.812m	457.857us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.719m	560.053us	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.747m	24.281ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.570s	52.435us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.275h	246.119ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.330s	13.574us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.670s	602.178us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.670s	602.178us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.150s	67.799us	5	5	100.00
		sram_ctrl_csr_rw	2.330s	22.459us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	43.250us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.320s	25.187us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.150s	67.799us	5	5	100.00
		sram_ctrl_csr_rw	2.330s	22.459us	20	20	100.00
		sram_ctrl_csr_aliasing	2.070s	43.250us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.320s	25.187us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.240s	6.253ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.310s	2.124us	0	5	0.00
		sram_ctrl_tl_intg_err	3.480s	1.672ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.310s	2.124us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.480s	1.672ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.747m	24.281ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	27.747m	24.281ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.330s	22.459us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.349m	3.196ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.349m	3.196ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.349m	3.196ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.720s	4.049ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.690s	191.890us	39	50	78.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.240s	6.253ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.640s	118.634us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.806m	159.765us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.806m	159.765us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.349m	3.196ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.310s	2.124us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.720s	4.049ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.310s	2.124us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.310s	2.124us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.806m	159.765us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.310s	2.124us	0	5	0.00
V2S		TOTAL			119	145	82.07
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.560m	1.786ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1163	1190	97.73

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	97.99	98.58	98.33

Failure Buckets

Offending 'reqfifo_rvalid' has 10 failures:
- Test sram_ctrl_mubi_enc_err has 10 failures.
  - 0.sram_ctrl_mubi_enc_err.105674664850564867814126561121347987372275347199245588034663434931887518554128
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  45184167 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  45184167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.sram_ctrl_mubi_enc_err.67201557167771385449225878248113379255200498177650122127545775694774198882762
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  29606450 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  29606450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:
- Test sram_ctrl_readback_err has 10 failures.
  - 3.sram_ctrl_readback_err.38289301390482555554001496853761508463344206690514098108123110746009407047266
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  56118917 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x6b) != exp (0x3d)
  UVM_INFO @  56118917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.sram_ctrl_readback_err.68147191385946532075415659969050882596243793991950069454771926137185690539475
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  93123951 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x69) != exp (0x29)
  UVM_INFO @  93123951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

Offending '(!$isunknown(rdata_o))' has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

0.sram_ctrl_sec_cm.76674644393230859429798414014881044618607154174139225481021949193644480874608
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   2123965 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2123965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.sram_ctrl_sec_cm.5401144270690743069609215903625178203846613679981577075077414880373630171795
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   1115451 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1115451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

1.sram_ctrl_sec_cm.88597557533241724812519840231618672524124183158298794079306740608320869672797
Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @  11201192 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  11201192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sram_ctrl_sec_cm.62306981292466764282911095008695572007969237574246476845759890287702803319455
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   6972582 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   6972582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 2.sram_ctrl_sec_cm.78731624918303277137864368936785802554897795531284634340324399652338652861075
    Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @  13963934 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @  13963934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 11.sram_ctrl_csr_mem_rw_with_rand_reset.9645472590338053105449475520339462525603391445989309333631677016258803419505
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  66686183 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  66686183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3405) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

27.sram_ctrl_mubi_enc_err.49649906479104385238264503016185741435116990609445512863487727705398980724159
Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @ 100663128 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3405) { a_addr: 'hf62f9528  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h4  a_user: 'h26daa  d_param: 'h0  d_source: 'hc  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 100663128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---