UART Simulation Results

Sunday May 18 2025 00:08:29 UTC

GitHub Revision: 54711bc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	35.320s	5.963ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.260s	18.439us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.410s	38.588us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.160s	262.352us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.440s	47.191us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.820s	23.055us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.410s	38.588us	20	20	100.00
		uart_csr_aliasing	2.440s	47.191us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.703m	75.399ms	50	50	100.00
V2	parity	uart_smoke	35.320s	5.963ms	50	50	100.00
		uart_tx_rx	3.703m	75.399ms	50	50	100.00
V2	parity_error	uart_intr	8.625m	262.785ms	50	50	100.00
		uart_rx_parity_err	7.420m	130.582ms	50	50	100.00
V2	watermark	uart_tx_rx	3.703m	75.399ms	50	50	100.00
		uart_intr	8.625m	262.785ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.114m	127.776ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.025m	173.483ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.757m	118.277ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.625m	262.785ms	50	50	100.00
V2	rx_break_err	uart_intr	8.625m	262.785ms	50	50	100.00
V2	rx_timeout	uart_intr	8.625m	262.785ms	50	50	100.00
V2	perf	uart_perf	16.258m	24.870ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.980s	10.434ms	50	50	100.00
V2	line_loopback	uart_loopback	27.980s	10.434ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.378m	385.291ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.261m	72.269ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	36.070s	6.172ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.284m	7.469ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.743m	145.036ms	50	50	100.00
V2	stress_all	uart_stress_all	18.288m	234.278ms	50	50	100.00
V2	alert_test	uart_alert_test	2.240s	46.647us	50	50	100.00
V2	intr_test	uart_intr_test	2.180s	38.421us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.850s	134.837us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.850s	134.837us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.260s	18.439us	5	5	100.00
		uart_csr_rw	2.410s	38.588us	20	20	100.00
		uart_csr_aliasing	2.440s	47.191us	5	5	100.00
		uart_same_csr_outstanding	2.470s	96.864us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.260s	18.439us	5	5	100.00
		uart_csr_rw	2.410s	38.588us	20	20	100.00
		uart_csr_aliasing	2.440s	47.191us	5	5	100.00
		uart_same_csr_outstanding	2.470s	96.864us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	2.360s	67.453us	5	5	100.00
		uart_tl_intg_err	2.990s	168.422us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.990s	168.422us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.674m	5.403ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1318	1320	99.85

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.17	98.25	91.55	--	98.14	100.00	99.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 37.uart_stress_all_with_rand_reset.102082017259098291844871452020202471403795305360768633230724615570789966071250
      Line 134, in log /nightly/runs/scratch/master/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5170127836 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 5170142021 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 5170142021 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 4/5
        UVM_INFO @ 5170148669 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 96.uart_stress_all_with_rand_reset.18962498946310378255547766046337385494053380680519719463568127239453501244491
      Line 141, in log /nightly/runs/scratch/master/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8941632362 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 9226426307 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/509
        UVM_INFO @ 9567512369 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/509
        UVM_INFO @ 9801555908 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/509
        UVM_INFO @ 9896723336 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/509