ADC_CTRL Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: `2a67071`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.380s	6.046ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.700s	769.312us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.040s	562.479us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.191m	53.570ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	8.460s	1.267ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.270s	602.125us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.040s	562.479us	20	20	100.00
		adc_ctrl_csr_aliasing	8.460s	1.267ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	23.512m	497.861ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.743m	484.627ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.379m	498.908ms	47	50	94.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.186m	487.271ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.987m	525.586ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.768m	605.732ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.348m	509.512ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	22.498m	620.989ms	30	50	60.00
V2	poweron_counter	adc_ctrl_poweron_counter	19.960s	5.286ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.749m	39.172ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	6.018m	120.710ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	24.384m	509.870ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	3.850s	533.006us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	4.160s	525.472us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.220s	597.339us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.220s	597.339us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.700s	769.312us	5	5	100.00
		adc_ctrl_csr_rw	4.040s	562.479us	20	20	100.00
		adc_ctrl_csr_aliasing	8.460s	1.267ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.470s	4.326ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.700s	769.312us	5	5	100.00
		adc_ctrl_csr_rw	4.040s	562.479us	20	20	100.00
		adc_ctrl_csr_aliasing	8.460s	1.267ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.470s	4.326ms	20	20	100.00
V2		TOTAL			711	740	96.08
V2S	tl_intg_err	adc_ctrl_sec_cm	14.690s	7.948ms	5	5	100.00
		adc_ctrl_tl_intg_err	32.280s	8.038ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	32.280s	8.038ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.180m	10.000s	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			886	920	96.30

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.64	99.11	96.45	100.00	100.00	99.01	98.06	90.88

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 19 failures:

Test adc_ctrl_clock_gating has 14 failures.

2.adc_ctrl_clock_gating.76071227340626682661264081918334262752553321637658546568274091860320193586422
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.adc_ctrl_clock_gating.76995832383995813758831289930380712951091593800097094610739450783646084933116
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

7.adc_ctrl_stress_all_with_rand_reset.5375083759546522407998698774144516075657895934193858320279324355070443631651
Line 152, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.adc_ctrl_stress_all_with_rand_reset.18455047154549152690622992114987245974508806820653105280452581218362350929923
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 2 failures.

10.adc_ctrl_stress_all.68372295020020529881187261230001140139256983930203344195411346902522552587900
Line 227, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.adc_ctrl_stress_all.111517524393039770213983446632708892446761273599980871677859473156132362782287
Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_both has 1 failures.

20.adc_ctrl_filters_both.98617868767032218200677801106183839991971893013130014465679872583349235962025
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:

Test adc_ctrl_clock_gating has 5 failures.

4.adc_ctrl_clock_gating.108722053256458505172548194919007511269565921468513174334840817408371189603687
Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 361753070192 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 361753070192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.adc_ctrl_clock_gating.33003338005547982858893608765911173237760428381714615475902039487205161038357
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 171351380267 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 171351380267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test adc_ctrl_stress_all has 2 failures.

8.adc_ctrl_stress_all.2584219035155016636885700618220322511967371276019051846256316027749998520345
Line 175, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 164846112061 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 164846112061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.adc_ctrl_stress_all.2665202884034611677270009223632941930036084173795211175303586940530866985021
Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 9049193148 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 9049193148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 5 failures:

Test adc_ctrl_clock_gating has 1 failures.

8.adc_ctrl_clock_gating.29017353632352539967829016635141482686446904783091525548870773301994534534066
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 172030264270 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 172030264270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_interrupt has 3 failures.

20.adc_ctrl_filters_interrupt.42654291857959089863924891704614502986461920166184983428066509404127432659724
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 327077508095 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 327077508095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.adc_ctrl_filters_interrupt.39493554279872087290798383522350186020680409088786568668448067120114624066660
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 413542503048 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 413542503048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_filters_both has 1 failures.

48.adc_ctrl_filters_both.96904904517379384001366331860565500177788269229479582706504274830597602038926
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 184982954076 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 184982954076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(np_sample_cnt_q == '0)' has 2 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 36.adc_ctrl_stress_all_with_rand_reset.106975545611724175996163999056023308428560892204863388301906051854822464979886
    Line 292, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 5820440666 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 5820440666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 48.adc_ctrl_stress_all_with_rand_reset.69340178005699303031173358168977020843683011056694299992551435039020925158222
    Line 261, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 6654910711 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 6654910711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 28.adc_ctrl_stress_all_with_rand_reset.77995277233653286537012489970727414514055000153733664966677543170397857369576
    Line 259, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41311004406 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 41311004406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```