AES/MASKED Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: `2a67071`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	39.000s	154.980us	1	1	100.00
V1	smoke	aes_smoke	32.000s	136.913us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	132.037us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	74.617us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	326.537us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	578.742us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	64.202us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	74.617us	20	20	100.00
		aes_csr_aliasing	7.000s	578.742us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	32.000s	136.913us	50	50	100.00
		aes_config_error	33.000s	1.322ms	50	50	100.00
		aes_stress	57.000s	5.198ms	50	50	100.00
V2	key_length	aes_smoke	32.000s	136.913us	50	50	100.00
		aes_config_error	33.000s	1.322ms	50	50	100.00
		aes_stress	57.000s	5.198ms	50	50	100.00
V2	back2back	aes_stress	57.000s	5.198ms	50	50	100.00
		aes_b2b	40.000s	642.145us	50	50	100.00
V2	backpressure	aes_stress	57.000s	5.198ms	50	50	100.00
V2	multi_message	aes_smoke	32.000s	136.913us	50	50	100.00
		aes_config_error	33.000s	1.322ms	50	50	100.00
		aes_stress	57.000s	5.198ms	50	50	100.00
		aes_alert_reset	1.033m	5.423ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	39.000s	66.545us	50	50	100.00
		aes_config_error	33.000s	1.322ms	50	50	100.00
		aes_alert_reset	1.033m	5.423ms	50	50	100.00
V2	trigger_clear_test	aes_clear	51.000s	2.864ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	44.000s	350.681us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.033m	5.423ms	50	50	100.00
V2	stress	aes_stress	57.000s	5.198ms	50	50	100.00
V2	sideload	aes_stress	57.000s	5.198ms	50	50	100.00
		aes_sideload	31.000s	152.974us	50	50	100.00
V2	deinitialization	aes_deinit	40.000s	67.610us	50	50	100.00
V2	stress_all	aes_stress_all	54.000s	4.595ms	10	10	100.00
V2	alert_test	aes_alert_test	31.000s	81.312us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	459.808us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	459.808us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	132.037us	5	5	100.00
		aes_csr_rw	6.000s	74.617us	20	20	100.00
		aes_csr_aliasing	7.000s	578.742us	5	5	100.00
		aes_same_csr_outstanding	6.000s	140.520us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	132.037us	5	5	100.00
		aes_csr_rw	6.000s	74.617us	20	20	100.00
		aes_csr_aliasing	7.000s	578.742us	5	5	100.00
		aes_same_csr_outstanding	6.000s	140.520us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	33.000s	457.750us	50	50	100.00
V2S	fault_inject	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	178.522us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	178.522us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	178.522us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	178.522us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	478.640us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	35.000s	2.829ms	5	5	100.00
		aes_tl_intg_err	8.000s	2.048ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	2.048ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.033m	5.423ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	178.522us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	32.000s	136.913us	50	50	100.00
		aes_stress	57.000s	5.198ms	50	50	100.00
		aes_alert_reset	1.033m	5.423ms	50	50	100.00
		aes_core_fi	33.000s	254.801us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	178.522us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	31.000s	261.013us	50	50	100.00
		aes_stress	57.000s	5.198ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	57.000s	5.198ms	50	50	100.00
		aes_sideload	31.000s	152.974us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	31.000s	261.013us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	31.000s	261.013us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	31.000s	261.013us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	31.000s	261.013us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	31.000s	261.013us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	57.000s	5.198ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	57.000s	5.198ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	33.000s	89.962us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	341	350	97.43
		aes_ctr_fi	31.000s	118.262us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	33.000s	89.962us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.002ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	33.000s	89.962us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_ctr_fi	31.000s	118.262us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	341	350	97.43
		aes_ctr_fi	31.000s	118.262us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.033m	5.423ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	341	350	97.43
		aes_ctr_fi	31.000s	118.262us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	341	350	97.43
		aes_ctr_fi	31.000s	118.262us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_ctr_fi	31.000s	118.262us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	33.000s	89.962us	50	50	100.00
		aes_control_fi	42.000s	10.014ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	341	350	97.43
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	46.000s	4.424ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.43	98.65	96.56	99.46	95.64	98.07	97.78	98.96	99.20

Failure Buckets

Job timed out after * minutes has 14 failures:
- Test aes_control_fi has 14 failures.
  - 1.aes_control_fi.93238202857125827394178562681621013511843081105617133931201859749497789389905
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 9.aes_control_fi.57540806350299447277902349089508562008718538430766172834646627674124680393578
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 27.aes_control_fi.87324937585614811536823468146738511745040007065903711804393042001325518285004
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10039727893 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039727893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 31.aes_control_fi.97618834373420432715943421902974903018821958831746334235134224256989204785571
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007144163 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007144163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 27.aes_cipher_fi.111793705372854744556159595483127714008866460134396764576352412616455088360109
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015011368 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015011368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_cipher_fi.21517376468007850068713616157509189569123616125827866837231731047124477442069
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10044125044 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10044125044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

3.aes_stress_all_with_rand_reset.13941342977366249305009050930201439707333455383962475526219856074821717159751
Line 507, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2036685715 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2036685715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.20793596982551463163148015910505943181410296824579464980038746048585109378718
Line 270, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 391016784 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 391016784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.2864192831167673101107215801594606749011271823548128393329373086358302056044
    Line 578, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4424413201 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4424413201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.aes_stress_all_with_rand_reset.80602821166719838381831348567319661401252797800950186108628708573905420172155
    Line 241, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 425740325 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 425740325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.5294595640096431727083801929881108973294109769198671304843204093660462390291
    Line 443, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3531516218 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3531516218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.55548254950533737940132460875980564953376288477209558310849012229382833765184
    Line 148, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 119989970 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 119989970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```