AES/UNMASKED Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: `2a67071`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	35.000s	107.736us	1	1	100.00
V1	smoke	aes_smoke	35.000s	100.486us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	95.427us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	69.564us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	986.703us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	530.024us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	95.202us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	69.564us	20	20	100.00
		aes_csr_aliasing	7.000s	530.024us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	35.000s	100.486us	50	50	100.00
		aes_config_error	35.000s	124.937us	50	50	100.00
		aes_stress	35.000s	406.322us	50	50	100.00
V2	key_length	aes_smoke	35.000s	100.486us	50	50	100.00
		aes_config_error	35.000s	124.937us	50	50	100.00
		aes_stress	35.000s	406.322us	50	50	100.00
V2	back2back	aes_stress	35.000s	406.322us	50	50	100.00
		aes_b2b	36.000s	93.161us	50	50	100.00
V2	backpressure	aes_stress	35.000s	406.322us	50	50	100.00
V2	multi_message	aes_smoke	35.000s	100.486us	50	50	100.00
		aes_config_error	35.000s	124.937us	50	50	100.00
		aes_stress	35.000s	406.322us	50	50	100.00
		aes_alert_reset	35.000s	166.106us	50	50	100.00
V2	failure_test	aes_man_cfg_err	34.000s	66.398us	50	50	100.00
		aes_config_error	35.000s	124.937us	50	50	100.00
		aes_alert_reset	35.000s	166.106us	50	50	100.00
V2	trigger_clear_test	aes_clear	36.000s	166.737us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	37.000s	128.803us	1	1	100.00
V2	reset_recovery	aes_alert_reset	35.000s	166.106us	50	50	100.00
V2	stress	aes_stress	35.000s	406.322us	50	50	100.00
V2	sideload	aes_stress	35.000s	406.322us	50	50	100.00
		aes_sideload	12.000s	57.569us	50	50	100.00
V2	deinitialization	aes_deinit	35.000s	65.669us	50	50	100.00
V2	stress_all	aes_stress_all	30.000s	684.825us	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	221.612us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	319.305us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	319.305us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	95.427us	5	5	100.00
		aes_csr_rw	6.000s	69.564us	20	20	100.00
		aes_csr_aliasing	7.000s	530.024us	5	5	100.00
		aes_same_csr_outstanding	6.000s	79.181us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	95.427us	5	5	100.00
		aes_csr_rw	6.000s	69.564us	20	20	100.00
		aes_csr_aliasing	7.000s	530.024us	5	5	100.00
		aes_same_csr_outstanding	6.000s	79.181us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	494.572us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	330	350	94.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	381.874us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	381.874us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	381.874us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	381.874us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	2.049ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	994.867us	5	5	100.00
		aes_tl_intg_err	8.000s	1.925ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	1.925ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	35.000s	166.106us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	381.874us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	35.000s	100.486us	50	50	100.00
		aes_stress	35.000s	406.322us	50	50	100.00
		aes_alert_reset	35.000s	166.106us	50	50	100.00
		aes_core_fi	25.000s	10.007ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	381.874us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	34.000s	71.919us	50	50	100.00
		aes_stress	35.000s	406.322us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	35.000s	406.322us	50	50	100.00
		aes_sideload	12.000s	57.569us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	34.000s	71.919us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	34.000s	71.919us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	34.000s	71.919us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	34.000s	71.919us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	34.000s	71.919us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	35.000s	406.322us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	35.000s	406.322us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	272.369us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	330	350	94.29
		aes_ctr_fi	6.000s	79.124us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	272.369us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	330	350	94.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.003ms	330	350	94.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	272.369us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_ctr_fi	6.000s	79.124us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	330	350	94.29
		aes_ctr_fi	6.000s	79.124us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	35.000s	166.106us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	330	350	94.29
		aes_ctr_fi	6.000s	79.124us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	330	350	94.29
		aes_ctr_fi	6.000s	79.124us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_ctr_fi	6.000s	79.124us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	272.369us	49	50	98.00
		aes_control_fi	51.000s	10.002ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	330	350	94.29
V2S		TOTAL			941	985	95.53
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	51.000s	7.255ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1548	1602	96.63

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.40	97.77	94.97	98.84	93.75	97.99	93.33	98.85	97.99

Failure Buckets

Job timed out after * minutes has 19 failures:
- Test aes_control_fi has 6 failures.
  - 6.aes_control_fi.55301270766752039615205909148771807405451177496288630697505708164645873425812
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 119.aes_control_fi.12228561634551062209615729530077528841995263190544992789968969167074856672869
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/119.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 4 more failures.
- Test aes_ctr_fi has 1 failures.
  - 23.aes_ctr_fi.75564072111968921693154497213815228078168980658831547287911593244530155456947
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/23.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_cipher_fi has 12 failures.
  - 38.aes_cipher_fi.48616988995126532053002974615988214023568266592859229036694873343285187745277
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/38.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 106.aes_cipher_fi.89313633427153780055527543577953590385731596554677909939135356591849343861107
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/106.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_control_fi has 14 failures.
  - 2.aes_control_fi.86270816115481438396161577959022417122436833469217577450061528914391990274176
    Line 145, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012289585 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012289585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_control_fi.55815077422775370709682192422403392006371211278199064182182758150718759098608
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002846731 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002846731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 45.aes_cipher_fi.90124969328769114787033200459538322000533644945263611633325772304129452541315
    Line 130, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/45.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10023986591 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023986591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 69.aes_cipher_fi.79048882195211121935557120140680764107639445463139757103536818290168131277184
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/69.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010348486 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010348486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.20923522867283973286672317021145008947247148132817752424822024182500115064459
Line 1183, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2909236121 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.keymgr_sideload_agent.sequencer.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2909236121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.65116648504348184785788264774706346849681361424980734109622912006917747995075
Line 572, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 294801535 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 294801535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 6.aes_stress_all_with_rand_reset.22448285717613311143158897062743081025990289565044921970762232962183042745012
    Line 587, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2045040134 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2045040134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.90903415846982799103402423403857071694212047944627825850915419556134413476444
    Line 217, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 486393544 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 486393544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.23186298861202043986771688596265457781323974898337413110148371388365122059981
    Line 389, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7254927678 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7254927678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 17.aes_core_fi.38308071732090222722031995441546908580796656808764297141893087155936233067669
    Line 146, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006547441 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006547441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

23.aes_fi.63194951133887344238049797760395410455686512112752799460435680902216126429905
Line 1547, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/23.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 10176287 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 10156287 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 10176287 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 10156287 PS)
  UVM_ERROR @  10176287 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_control_fi_vseq.sv:68) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_control_fi has 1 failures.
  - 299.aes_control_fi.76776753808371745363159960571640376813188317710158164176436253563208371502116
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/299.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10045232095 ps: (aes_control_fi_vseq.sv:68) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10045232095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```