CSRNG Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	183.524us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	21.927us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	160.488us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	28.000s	1.469ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	303.988us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	512.722us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	160.488us	20	20	100.00
		csrng_csr_aliasing	7.000s	303.988us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	24.000s	1.912ms	200	200	100.00
V2	alerts	csrng_alert	1.083m	3.704ms	500	500	100.00
V2	err	csrng_err	7.000s	23.832us	500	500	100.00
V2	cmds	csrng_cmds	10.150m	47.445ms	50	50	100.00
V2	life cycle	csrng_cmds	10.150m	47.445ms	50	50	100.00
V2	stress_all	csrng_stress_all	30.033m	123.934ms	47	50	94.00
V2	intr_test	csrng_intr_test	6.000s	15.577us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	117.336us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	23.000s	1.588ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	23.000s	1.588ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	21.927us	5	5	100.00
		csrng_csr_rw	7.000s	160.488us	20	20	100.00
		csrng_csr_aliasing	7.000s	303.988us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	112.641us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	21.927us	5	5	100.00
		csrng_csr_rw	7.000s	160.488us	20	20	100.00
		csrng_csr_aliasing	7.000s	303.988us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	112.641us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_sec_cm	12.000s	824.467us	5	5	100.00
		csrng_tl_intg_err	15.000s	767.518us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	130.646us	50	50	100.00
		csrng_csr_rw	7.000s	160.488us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	3.704ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	30.033m	123.934ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	3.704ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	30.033m	123.934ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	3.704ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	767.518us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
		csrng_sec_cm	12.000s	824.467us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	24.000s	1.912ms	200	200	100.00
		csrng_err	7.000s	23.832us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.233m	2.189ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1617	1630	99.20

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.72	98.61	96.62	99.94	97.36	92.08	100.00	97.36	90.36

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.34292690384381250391824807531120502853467116303923114702353063536169268351835
      Line 113, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 825820477 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 825820477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.37434311852152903568061158101297525302726964315304726128178208065740735652164
      Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 102044456 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 102044456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 5.csrng_stress_all.45282101392130671297121527005248496853588261187667545339510452990051174265790
      Line 144, in log /nightly/runs/scratch/master/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log

        UVM_ERROR @ 6399592028 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 6399592028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.csrng_stress_all.90357156272893515938224494869695358780754533623114642823514674060606879766324
      Line 149, in log /nightly/runs/scratch/master/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log

        UVM_ERROR @ 12613140153 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 12613140153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.