EDN Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.690s 134.578us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.580s 21.274us 5 5 100.00
V1 csr_rw edn_csr_rw 2.420s 16.887us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.620s 259.462us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.820s 24.789us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.440s 29.765us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.420s 16.887us 20 20 100.00
edn_csr_aliasing 2.820s 24.789us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.679m 9.101ms 300 300 100.00
V2 csrng_commands edn_genbits 2.679m 9.101ms 300 300 100.00
V2 genbits edn_genbits 2.679m 9.101ms 300 300 100.00
V2 interrupts edn_intr 2.750s 21.228us 50 50 100.00
V2 alerts edn_alert 3.050s 282.069us 200 200 100.00
V2 errs edn_err 2.960s 33.431us 100 100 100.00
V2 disable edn_disable 2.580s 20.801us 50 50 100.00
edn_disable_auto_req_mode 3.030s 36.677us 50 50 100.00
V2 stress_all edn_stress_all 7.240s 765.052us 50 50 100.00
V2 intr_test edn_intr_test 2.510s 18.249us 50 50 100.00
V2 alert_test edn_alert_test 2.550s 32.442us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.740s 234.973us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.740s 234.973us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.580s 21.274us 5 5 100.00
edn_csr_rw 2.420s 16.887us 20 20 100.00
edn_csr_aliasing 2.820s 24.789us 5 5 100.00
edn_same_csr_outstanding 2.800s 24.751us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.580s 21.274us 5 5 100.00
edn_csr_rw 2.420s 16.887us 20 20 100.00
edn_csr_aliasing 2.820s 24.789us 5 5 100.00
edn_same_csr_outstanding 2.800s 24.751us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 10.850s 1.157ms 5 5 100.00
edn_tl_intg_err 6.450s 208.282us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.630s 28.956us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.050s 282.069us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 10.850s 1.157ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 10.850s 1.157ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 10.850s 1.157ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 10.850s 1.157ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.050s 282.069us 200 200 100.00
edn_sec_cm 10.850s 1.157ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.050s 282.069us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 6.450s 208.282us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.738m 18.833ms 27 50 54.00
V3 TOTAL 27 50 54.00
TOTAL 1107 1130 97.96

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.10 98.32 94.29 97.02 93.60 96.33 99.78 93.32

Failure Buckets