ENTROPY_SRC Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 24.000s 27.554us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 9.000s 39.086us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 20.479us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 779.097us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 10.000s 261.615us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 6.000s 43.208us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 20.479us 20 20 100.00
entropy_src_csr_aliasing 10.000s 261.615us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 24.000s 27.554us 50 50 100.00
entropy_src_rng 5.933m 14.019ms 23 300 7.67
entropy_src_fw_ov 9.717m 19.018ms 182 300 60.67
V2 firmware_mode entropy_src_fw_ov 9.717m 19.018ms 182 300 60.67
V2 rng_mode entropy_src_rng 5.933m 14.019ms 23 300 7.67
V2 rng_max_rate entropy_src_rng_max_rate 4.883m 9.033ms 12 400 3.00
V2 health_checks entropy_src_rng 5.933m 14.019ms 23 300 7.67
V2 conditioning entropy_src_rng 5.933m 14.019ms 23 300 7.67
V2 interrupts entropy_src_rng 5.933m 14.019ms 23 300 7.67
entropy_src_intr 35.000s 2.677ms 50 50 100.00
V2 alerts entropy_src_rng 5.933m 14.019ms 23 300 7.67
entropy_src_functional_alerts 27.000s 56.693us 50 50 100.00
V2 stress_all entropy_src_stress_all 8.550m 19.126ms 49 50 98.00
V2 functional_errors entropy_src_functional_errors 6.767m 10.012ms 965 1000 96.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 32.000s 673.219us 50 50 100.00
V2 intr_test entropy_src_intr_test 10.000s 21.825us 50 50 100.00
V2 alert_test entropy_src_alert_test 25.000s 25.658us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 13.000s 735.150us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 13.000s 735.150us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 9.000s 39.086us 5 5 100.00
entropy_src_csr_rw 8.000s 20.479us 20 20 100.00
entropy_src_csr_aliasing 10.000s 261.615us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 142.563us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 9.000s 39.086us 5 5 100.00
entropy_src_csr_rw 8.000s 20.479us 20 20 100.00
entropy_src_csr_aliasing 10.000s 261.615us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 142.563us 20 20 100.00
V2 TOTAL 1521 2340 65.00
V2S tl_intg_err entropy_src_sec_cm 8.000s 1.248ms 5 5 100.00
entropy_src_tl_intg_err 12.000s 106.201us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.933m 14.019ms 23 300 7.67
entropy_src_cfg_regwen 25.000s 65.052us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.933m 14.019ms 23 300 7.67
V2S sec_cm_config_redun entropy_src_rng 5.933m 14.019ms 23 300 7.67
V2S sec_cm_intersig_mubi entropy_src_rng 5.933m 14.019ms 23 300 7.67
entropy_src_fw_ov 9.717m 19.018ms 182 300 60.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 6.767m 10.012ms 965 1000 96.50
entropy_src_sec_cm 8.000s 1.248ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 6.767m 10.012ms 965 1000 96.50
entropy_src_sec_cm 8.000s 1.248ms 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.933m 14.019ms 23 300 7.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 6.767m 10.012ms 965 1000 96.50
entropy_src_sec_cm 8.000s 1.248ms 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 6.767m 10.012ms 965 1000 96.50
entropy_src_sec_cm 8.000s 1.248ms 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 6.767m 10.012ms 965 1000 96.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 27.000s 56.693us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 12.000s 106.201us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 3.200m 8.081ms 6 50 12.00
V3 TOTAL 6 50 12.00
TOTAL 1707 2570 66.42

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.47 98.19 95.43 98.37 95.46 96.62 96.88 91.01 89.72

Failure Buckets