HMAC Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.800s	5.711ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.390s	19.511us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.290s	150.613us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.710s	10.554ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.370s	443.253us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	50.410s	4.652ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.290s	150.613us	20	20	100.00
		hmac_csr_aliasing	7.370s	443.253us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.464m	68.072ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.422m	11.127ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.935m	11.325ms	30	30	100.00
		hmac_test_sha384_vectors	8.208m	57.852ms	75	75	100.00
		hmac_test_sha512_vectors	8.456m	57.811ms	75	75	100.00
		hmac_test_hmac256_vectors	15.590s	2.133ms	50	50	100.00
		hmac_test_hmac384_vectors	18.210s	378.967us	60	60	100.00
		hmac_test_hmac512_vectors	20.570s	448.174us	75	75	100.00
V2	burst_wr	hmac_burst_wr	36.240s	8.275ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	22.499m	32.205ms	10	10	100.00
V2	error	hmac_error	1.867m	3.085ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.336m	9.399ms	10	10	100.00
V2	save_and_restore	hmac_smoke	15.800s	5.711ms	10	10	100.00
		hmac_long_msg	1.464m	68.072ms	10	10	100.00
		hmac_back_pressure	1.422m	11.127ms	25	25	100.00
		hmac_datapath_stress	22.499m	32.205ms	10	10	100.00
		hmac_burst_wr	36.240s	8.275ms	50	50	100.00
		hmac_stress_all	39.523m	127.932ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.800s	5.711ms	10	10	100.00
		hmac_long_msg	1.464m	68.072ms	10	10	100.00
		hmac_back_pressure	1.422m	11.127ms	25	25	100.00
		hmac_datapath_stress	22.499m	32.205ms	10	10	100.00
		hmac_wipe_secret	1.336m	9.399ms	10	10	100.00
		hmac_test_sha256_vectors	3.935m	11.325ms	30	30	100.00
		hmac_test_sha384_vectors	8.208m	57.852ms	75	75	100.00
		hmac_test_sha512_vectors	8.456m	57.811ms	75	75	100.00
		hmac_test_hmac256_vectors	15.590s	2.133ms	50	50	100.00
		hmac_test_hmac384_vectors	18.210s	378.967us	60	60	100.00
		hmac_test_hmac512_vectors	20.570s	448.174us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.800s	5.711ms	10	10	100.00
		hmac_long_msg	1.464m	68.072ms	10	10	100.00
		hmac_back_pressure	1.422m	11.127ms	25	25	100.00
		hmac_datapath_stress	22.499m	32.205ms	10	10	100.00
		hmac_burst_wr	36.240s	8.275ms	50	50	100.00
		hmac_error	1.867m	3.085ms	10	10	100.00
		hmac_wipe_secret	1.336m	9.399ms	10	10	100.00
		hmac_test_sha256_vectors	3.935m	11.325ms	30	30	100.00
		hmac_test_sha384_vectors	8.208m	57.852ms	75	75	100.00
		hmac_test_sha512_vectors	8.456m	57.811ms	75	75	100.00
		hmac_test_hmac256_vectors	15.590s	2.133ms	50	50	100.00
		hmac_test_hmac384_vectors	18.210s	378.967us	60	60	100.00
		hmac_test_hmac512_vectors	20.570s	448.174us	75	75	100.00
		hmac_stress_all	39.523m	127.932ms	50	50	100.00
V2	stress_all	hmac_stress_all	39.523m	127.932ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.080s	32.471us	50	50	100.00
V2	intr_test	hmac_intr_test	2.180s	14.064us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.950s	585.159us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.950s	585.159us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.390s	19.511us	5	5	100.00
		hmac_csr_rw	2.290s	150.613us	20	20	100.00
		hmac_csr_aliasing	7.370s	443.253us	5	5	100.00
		hmac_same_csr_outstanding	3.840s	115.771us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.390s	19.511us	5	5	100.00
		hmac_csr_rw	2.290s	150.613us	20	20	100.00
		hmac_csr_aliasing	7.370s	443.253us	5	5	100.00
		hmac_same_csr_outstanding	3.840s	115.771us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.520s	125.163us	5	5	100.00
		hmac_tl_intg_err	5.530s	1.742ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.530s	1.742ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.800s	5.711ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	10.100s	709.154us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	9.775m	6.678ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.520s	65.217us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.67	100.00	97.31	100.00	97.06	100.00	100.00	47.30