I2C Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: `2a67071`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.757m	10.808ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	44.120s	5.133ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.250s	26.685us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.340s	37.170us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.410s	480.172us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.820s	342.089us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.830s	30.012us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.340s	37.170us	20	20	100.00
		i2c_csr_aliasing	2.820s	342.089us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	15.430s	808.815us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	47.011m	76.208ms	14	50	28.00
V2	host_maxperf	i2c_host_perf	42.849m	73.783ms	50	50	100.00
V2	host_override	i2c_host_override	2.290s	79.102us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.905m	20.619ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	3.155m	10.826ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	3.060s	1.760ms	50	50	100.00
		i2c_host_fifo_fmt_empty	30.020s	567.631us	50	50	100.00
		i2c_host_fifo_reset_rx	13.540s	479.314us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.646m	14.707ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	38.950s	853.864us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	6.100s	152.403us	16	50	32.00
V2	target_glitch	i2c_target_glitch	14.580s	2.292ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	16.382m	69.521ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	10.000s	3.737ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.545m	1.865ms	50	50	100.00
		i2c_target_intr_smoke	12.840s	3.120ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.950s	350.689us	50	50	100.00
		i2c_target_fifo_reset_tx	3.440s	288.326us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	26.329m	72.054ms	50	50	100.00
		i2c_target_stress_rd	1.545m	1.865ms	50	50	100.00
		i2c_target_intr_stress_wr	7.702m	24.365ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	12.030s	5.069ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.187m	4.530ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	10.490s	1.698ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	43.910s	10.144ms	20	50	40.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.830s	1.350ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.370s	152.517us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	42.849m	73.783ms	50	50	100.00
		i2c_host_perf_precise	12.993m	23.188ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	38.950s	853.864us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	27.960s	1.975ms	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.680s	2.117ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.310s	524.338us	50	50	100.00
		i2c_target_nack_txstretch	3.300s	229.173us	32	50	64.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	26.460s	720.337us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	5.130s	2.375ms	50	50	100.00
V2	alert_test	i2c_alert_test	2.180s	22.326us	50	50	100.00
V2	intr_test	i2c_intr_test	2.300s	19.293us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.670s	542.184us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.670s	542.184us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.250s	26.685us	5	5	100.00
		i2c_csr_rw	2.340s	37.170us	20	20	100.00
		i2c_csr_aliasing	2.820s	342.089us	5	5	100.00
		i2c_same_csr_outstanding	2.530s	57.588us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.250s	26.685us	5	5	100.00
		i2c_csr_rw	2.340s	37.170us	20	20	100.00
		i2c_csr_aliasing	2.820s	342.089us	5	5	100.00
		i2c_same_csr_outstanding	2.530s	57.588us	20	20	100.00
V2		TOTAL			1667	1792	93.02
V2S	tl_intg_err	i2c_tl_intg_err	3.350s	508.542us	20	20	100.00
		i2c_sec_cm	2.520s	72.008us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.350s	508.542us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	58.590s	13.281ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.960s	1.061ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	28.430s	1.883ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1847	2042	90.45

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.05	97.32	89.78	74.17	72.02	94.25	98.52	90.27

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 59 failures:

Test i2c_host_stress_all has 31 failures.

0.i2c_host_stress_all.31087172927832757936165274692513834285765844326860026981672635830410675309103
Line 117, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 9090625578 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2123630

1.i2c_host_stress_all.5864112990135464226075371127301332176913850079869602488703093662206129024112
Line 178, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 45354138677 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3062942

... and 29 more failures.

Test i2c_host_mode_toggle has 28 failures.

0.i2c_host_mode_toggle.109575238802202278003827928553256139648390376070822008539623574903022603900600
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 247385004 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @100717

3.i2c_host_mode_toggle.66874512485413897108969746133219045953222217254178382375588189068405579113518
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 238408877 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @23671

... and 26 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
- Test i2c_target_hrst has 30 failures.
  - 1.i2c_target_hrst.76490308135298162670209875294108486501512818252918736465118744723627989178987
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10004827803 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10004827803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_hrst.36789530679903362908237796421191182049861581560085958733819766690972107545474
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10608700687 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10608700687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
- Test i2c_target_unexp_stop has 27 failures.
  - 1.i2c_target_unexp_stop.19232706835110500043828250024243040384315003273570739889532939095991220593575
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 208258049 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 93 [0x5d])
  UVM_INFO @ 208258049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.15022515036167670830125094976628726127649591185163585013251973802642801043264
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 328091371 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 10 [0xa])
  UVM_INFO @ 328091371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 25 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
- Test i2c_target_unexp_stop has 20 failures.
  - 0.i2c_target_unexp_stop.114103081993676162854978955710247430306889431486487160565404220139135611135829
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  66579350 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  66579350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_unexp_stop.31442154401341255448658212908363249885435482614362792717266929949897643166261
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 200056257 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 200056257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
- Test i2c_target_nack_txstretch has 18 failures.
  - 0.i2c_target_nack_txstretch.91879425107308520910011460541801870633164248901367288022179719363642977977260
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 138728038 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 138728038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_nack_txstretch.22429347143510254847763455995770164190059104513399778944130962799932351535713
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 369627250 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 369627250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.47165283006470987781460926565197063954143044707709914833286104161039614941053
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 565998099 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 565998099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.90928727634820965998320157836236462472222086744320349971032594955529267932210
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1137071525 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1137071525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

1.i2c_target_stress_all_with_rand_reset.5529845965395726194630291459320589937288891231307648243869217824803784520163
Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 964660837 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 964660837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.84463116595662731454655719653783091233816965941922662929973939616196718461184
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 333524584 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 333524584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 5 failures:

Test i2c_host_mode_toggle has 5 failures.

5.i2c_host_mode_toggle.85805521097447170724319131854265417541589735189915728063046046463479939270582
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  57007777 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

23.i2c_host_mode_toggle.72475424479578157570858562196680375644433174910677762112103496606783267871532
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 152263920 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 3 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

15.i2c_host_stress_all.99656175323104257785114255091676546533534324363837595209954617098983279728594
Line 258, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 94594096625 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @6462368

22.i2c_host_stress_all.52134974041456834024748389689644689080976930149988008501835328112272736467197
Line 190, in log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 34781584442 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @6330088

... and 3 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 18.i2c_target_stretch.45641274025737317778160355574513484275238424615282936893461177152531254972292
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10045916470 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10045916470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 29.i2c_target_stretch.113521562576067797652929341660731415535828554760484807786849294587978985113661
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/29.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001215663 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001215663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 0.i2c_target_stress_all_with_rand_reset.104027726431703303976432432192001740796770375477054649036373552723546686934885
    Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 627529735 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 627529735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_stress_all_with_rand_reset.90716881881082104706650991572940007925414244539212848936809055956563178779156
    Line 116, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1883163034 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1883163034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:

Test i2c_target_unexp_stop has 3 failures.

5.i2c_target_unexp_stop.46106956851455104081494856629641593721678596707170172425277595226796177942756
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 637369301 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 637369301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.i2c_target_unexp_stop.69112764906702587895822293950465872983342261415707551050769224060205239802807
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 512120880 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 512120880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_tx_stretch_ctrl has 2 failures.
  - 5.i2c_target_tx_stretch_ctrl.65365704690881841422493181691680999131505620421971723732149954770388377541260
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 7.i2c_target_tx_stretch_ctrl.73217531548622026317518450412239736456793348754303446288417436400412733220812
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 44.i2c_target_fifo_watermarks_tx.81251925402410114906267078767994873678891378330470992561472660332683926526843
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 46.i2c_host_mode_toggle.13217508432241302672545970554991874142876032736968285494035904092973419145952
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/46.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 172768792 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xa0808494, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 172768792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```