KEYMGR Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: `2a67071`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	23.370s	3.198ms	50	50	100.00
V1	random	keymgr_random	45.010s	5.717ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.650s	36.383us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.600s	45.636us	15	20	75.00
V1	csr_bit_bash	keymgr_csr_bit_bash	12.930s	2.660ms	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	11.390s	751.872us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.060s	129.968us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.600s	45.636us	15	20	75.00
		keymgr_csr_aliasing	11.390s	751.872us	5	5	100.00
V1		TOTAL			146	155	94.19
V2	cfgen_during_op	keymgr_cfg_regwen	1.259m	1.885ms	50	50	100.00
V2	sideload	keymgr_sideload	36.690s	4.639ms	50	50	100.00
		keymgr_sideload_kmac	26.910s	8.388ms	50	50	100.00
		keymgr_sideload_aes	43.840s	6.093ms	50	50	100.00
		keymgr_sideload_otbn	25.810s	1.577ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	36.150s	1.510ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	29.200s	1.438ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	5.950s	510.069us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.149m	9.481ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	35.930s	4.952ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	21.000s	2.872ms	50	50	100.00
V2	stress_all	keymgr_stress_all	8.542m	248.006ms	49	50	98.00
V2	intr_test	keymgr_intr_test	2.150s	12.273us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.650s	133.911us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.210s	1.120ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.210s	1.120ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.650s	36.383us	5	5	100.00
		keymgr_csr_rw	2.600s	45.636us	15	20	75.00
		keymgr_csr_aliasing	11.390s	751.872us	5	5	100.00
		keymgr_same_csr_outstanding	4.440s	104.553us	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.650s	36.383us	5	5	100.00
		keymgr_csr_rw	2.600s	45.636us	15	20	75.00
		keymgr_csr_aliasing	11.390s	751.872us	5	5	100.00
		keymgr_same_csr_outstanding	4.440s	104.553us	14	20	70.00
V2		TOTAL			730	740	98.65
V2S	sec_cm_additional_check	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
		keymgr_tl_intg_err	7.100s	1.099ms	14	20	70.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.520s	806.634us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.520s	806.634us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.520s	806.634us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.520s	806.634us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	11.970s	851.184us	12	20	60.00
V2S	prim_count_check	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.100s	1.099ms	14	20	70.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.520s	806.634us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.259m	1.885ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	45.010s	5.717ms	50	50	100.00
		keymgr_csr_rw	2.600s	45.636us	15	20	75.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	45.010s	5.717ms	50	50	100.00
		keymgr_csr_rw	2.600s	45.636us	15	20	75.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	45.010s	5.717ms	50	50	100.00
		keymgr_csr_rw	2.600s	45.636us	15	20	75.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	29.200s	1.438ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	35.930s	4.952ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	35.930s	4.952ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	45.010s	5.717ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	28.220s	3.890ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	45.950s	1.387ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	29.200s	1.438ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	45.950s	1.387ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	45.950s	1.387ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	45.950s	1.387ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.330s	674.827us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	45.950s	1.387ms	50	50	100.00
V2S		TOTAL			151	165	91.52
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	24.210s	2.535ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1057	1110	95.23

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.10	98.18	98.40	100.00	99.10	98.63	91.11

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 29 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 8 failures.

1.keymgr_shadow_reg_errors_with_csr_rw.31590000892858128672883480531216986679882419953623870371086655584258022353566
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  21487875 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  21487875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_shadow_reg_errors_with_csr_rw.112954655054310684706888438115015223313922723573752914456371301031489968313992
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @   8971648 ps: (keymgr_csr_assert_fpv.sv:429) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @   8971648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_csr_mem_rw_with_rand_reset has 3 failures.

2.keymgr_csr_mem_rw_with_rand_reset.33712497257245174220524395523986480083487846874869332409924977633863183896325
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @  42106595 ps: (keymgr_csr_assert_fpv.sv:459) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @  42106595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.keymgr_csr_mem_rw_with_rand_reset.86137481094772545274673844767884908357102522291593209747565909870402171413296
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @  55447705 ps: (keymgr_csr_assert_fpv.sv:429) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @  55447705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_csr_bit_bash has 1 failures.

3.keymgr_csr_bit_bash.82534492727991555772206925747259007404189310067450342399376918823425617778012
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @ 2659593878 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @ 2659593878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_tl_intg_err has 6 failures.

4.keymgr_tl_intg_err.83758276693597630160757259393228228734547236038046822907481230907790959573742
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  22422427 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  22422427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_tl_intg_err.97349560060501559383252826615167529359960724646406603282276686162831166241154
Line 100, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  26125092 ps: (keymgr_csr_assert_fpv.sv:404) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  26125092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_rw has 5 failures.

6.keymgr_csr_rw.91566241474299433280677892155771553862289763361539229763756132947189105465811
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  42491165 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  42491165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_csr_rw.56824589746618348154158239711111624726952095643790423176463170075487831431860
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  11279671 ps: (keymgr_csr_assert_fpv.sv:409) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  11279671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 1.keymgr_stress_all_with_rand_reset.56110836691432405292740495416784825664027412093200354576114571160762459875414
    Line 354, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 912350833 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 912350833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.28239243749201117374578188333651100059954978846161982088490995847979175383822
    Line 158, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 210984297 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 210984297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_stress_all has 1 failures.
  - 28.keymgr_stress_all.70917119640023360101848683432367308905770960468334407361456101154543430208998
    Line 355, in log /nightly/runs/scratch/master/keymgr-sim-vcs/28.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 288805862 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 288805862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 30.keymgr_hwsw_invalid_input.91751534187425907649734712991315497010922079142471734794962118816137494259126
    Line 375, in log /nightly/runs/scratch/master/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  84159112 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  84159112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 15.keymgr_kmac_rsp_err.104987607425849744903689847690738355782051798476161717524307128132712647922438
    Line 372, in log /nightly/runs/scratch/master/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @ 121998379 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @ 121998379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 20.keymgr_stress_all_with_rand_reset.8166859039438166589186985030742027113407410126455673383613684208588756861071
    Line 1083, in log /nightly/runs/scratch/master/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1333048128 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1889962325 [0x70a68955] vs 1889962325 [0x70a68955]) reg name: keymgr_reg_block.sw_share0_output_6
  UVM_INFO @ 1333048128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 23.keymgr_lc_disable.105540407355314825327418597226329424391653901394966247788872316267382648161754
    Line 223, in log /nightly/runs/scratch/master/keymgr-sim-vcs/23.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  46138900 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (4068025417 [0xf2792449] vs 4068025417 [0xf2792449]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @  46138900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```