KMAC/MASKED Simulation Results

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: `2a67071`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.498m	5.207ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.510s	98.901us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.730s	31.705us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.790s	1.278ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.490s	538.147us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.000s	71.731us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.730s	31.705us	20	20	100.00
		kmac_csr_aliasing	11.490s	538.147us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.210s	13.553us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.990s	156.090us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.797m	89.302ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.230m	39.938ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.315m	65.250ms	5	5	100.00
		kmac_test_vectors_sha3_256	41.669m	338.458ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.331m	67.417ms	5	5	100.00
		kmac_test_vectors_sha3_512	15.979m	18.884ms	5	5	100.00
		kmac_test_vectors_shake_128	40.401m	469.311ms	5	5	100.00
		kmac_test_vectors_shake_256	35.892m	395.687ms	5	5	100.00
		kmac_test_vectors_kmac	4.490s	350.316us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.660s	149.600us	5	5	100.00
V2	sideload	kmac_sideload	8.749m	66.040ms	50	50	100.00
V2	app	kmac_app	6.600m	12.922ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.921m	33.352ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.382m	67.056ms	50	50	100.00
V2	error	kmac_error	7.963m	13.453ms	50	50	100.00
V2	key_error	kmac_key_error	18.220s	5.861ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.560s	125.666us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.020s	9.135ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	19.540s	3.474ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.163m	6.749ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.320s	7.657ms	50	50	100.00
V2	stress_all	kmac_stress_all	45.034m	809.567ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.370s	21.839us	50	50	100.00
V2	alert_test	kmac_alert_test	2.300s	211.156us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.090s	290.631us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.090s	290.631us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.510s	98.901us	5	5	100.00
		kmac_csr_rw	2.730s	31.705us	20	20	100.00
		kmac_csr_aliasing	11.490s	538.147us	5	5	100.00
		kmac_same_csr_outstanding	3.570s	138.636us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.510s	98.901us	5	5	100.00
		kmac_csr_rw	2.730s	31.705us	20	20	100.00
		kmac_csr_aliasing	11.490s	538.147us	5	5	100.00
		kmac_same_csr_outstanding	3.570s	138.636us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.400s	138.735us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.400s	138.735us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.400s	138.735us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.400s	138.735us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.720s	836.094us	12	20	60.00
V2S	tl_intg_err	kmac_sec_cm	1.095m	5.821ms	5	5	100.00
		kmac_tl_intg_err	6.030s	358.470us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.030s	358.470us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.320s	7.657ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.498m	5.207ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.749m	66.040ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.400s	138.735us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.095m	5.821ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.095m	5.821ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.095m	5.821ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.498m	5.207ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.320s	7.657ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.095m	5.821ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.498m	15.031ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.498m	5.207ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.822m	5.240ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			926	940	98.51

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.32	99.03	94.47	99.89	79.58	97.03	99.37	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 11 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

0.kmac_shadow_reg_errors_with_csr_rw.43901825782199524666819086644317845104663392732156965092513904034598360792190
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
  UVM_ERROR @ 579623202 ps: (kmac_csr_assert_fpv.sv:510) [ASSERT FAILED] prefix_3_rd_A
  UVM_INFO @ 579623202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors_with_csr_rw.64879940557541938553756594602153155905566619989950407755061644543848415767160
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  41870345 ps: (kmac_csr_assert_fpv.sv:505) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  41870345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 4 failures.

0.kmac_tl_intg_err.17256933740087251429873042743096577006724709178503738246453904494975793415265
Line 101, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @ 144455082 ps: (kmac_csr_assert_fpv.sv:495) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @ 144455082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_tl_intg_err.39507969623654652395830717151068238585842822795432649791302871344490525167948
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @   8028111 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @   8028111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 2.kmac_stress_all_with_rand_reset.20825456597737222546944545492310571030160439414862775841542900773124464610872
    Line 139, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1474704273 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1474704273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.68807318301825987493362136501817618451762210699043051188246056315982382094506
    Line 99, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 371810920 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 371810920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 19.kmac_shadow_reg_errors_with_csr_rw.84160475712392327659772488263481968623051523457047231708874162570923110992370
    Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 193907389 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (378575254 [0x16909996] vs 2420253874 [0x904224b2]) Regname: kmac_reg_block.prefix_8.prefix_0 reset value: 0x0
  UVM_INFO @ 193907389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```